Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "cavium/octeon plus/cn5734-1000bg1217-ssp"
(Created page with "{{cavium title|CN5734-1000 SSP}} {{mpu | name = Cavium CN5734-1000 SSP | no image = | image = Octeon CN57xx.svg | image size...") |
|||
| Line 83: | Line 83: | ||
| package 0 pins = 1217 | | package 0 pins = 1217 | ||
| package 0 pitch = | | package 0 pitch = | ||
| − | | package 0 width = | + | | package 0 width = 40 mm |
| − | | package 0 length = | + | | package 0 length = 40 mm |
| package 0 height = | | package 0 height = | ||
| socket 0 = BGA-1217 | | socket 0 = BGA-1217 | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
}} | }} | ||
| + | '''CN5734-1000 SSP''' is a {{arch|64}} [[hexa-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates six {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration. | ||
Revision as of 23:05, 28 December 2016
Template:mpu CN5734-1000 SSP is a 64-bit hexa-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates six cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.
Facts about "CN5734-1000 SSP - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN5734-1000 SSP - Cavium#io + |
| has ecc memory support | true + |
| has hardware accelerators for cryptography | true + |
| has hardware accelerators for data compression | true + |
| has hardware accelerators for data decompression | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| has hardware raid 5 support | true + |
| has hardware raid 6 support | true + |
| l1$ size | 288 KiB (294,912 B, 0.281 MiB) + |
| l1d$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
| l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 8 + |
| supported memory type | DDR2-800 + |