Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "cavium/octeon plus/cn5734-900bg1217-ssp"
(Created page with "{{cavium title|CN5734-900 SSP}} {{mpu | name = Cavium CN5734-900 SSP | no image = | image = Octeon CN57xx.svg | image size =...") |
|||
| Line 83: | Line 83: | ||
| package 0 pins = 1217 | | package 0 pins = 1217 | ||
| package 0 pitch = | | package 0 pitch = | ||
| − | | package 0 width = | + | | package 0 width = 40 mm |
| − | | package 0 length = | + | | package 0 length = 40 mm |
| package 0 height = | | package 0 height = | ||
| socket 0 = BGA-1217 | | socket 0 = BGA-1217 | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
}} | }} | ||
| + | '''CN5734-900 SSP''' is a {{arch|64}} [[hexa-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates six {{cavium|cnMIPS|l=arch}} cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration. | ||
Revision as of 23:03, 28 December 2016
Template:mpu CN5734-900 SSP is a 64-bit hexa-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates six cnMIPS cores, operates at 900 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.