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Difference between revisions of "cavium/octeon plus/cn5734-800bg1217-ssp"
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| + | '''CN5734-800 SSP''' is a {{arch|64}} [[hexa-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates six {{cavium|cnMIPS|l=arch}} cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration. | ||
Revision as of 23:53, 28 December 2016
Template:mpu CN5734-800 SSP is a 64-bit hexa-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates six cnMIPS cores, operates at 800 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.
Facts about "CN5734-800 SSP - Cavium"
