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Difference between revisions of "cavium/octeon/cn3010-400bg525-cp"
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The '''CN3010-400 CP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 400 MHz and dissipates 3 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the {{\\|cn3005-400bg350-cp|CN3005 equivalent}}, double DDR2 memory access, as well as support for TDM/PCM (VoIP support). | The '''CN3010-400 CP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 400 MHz and dissipates 3 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the {{\\|cn3005-400bg350-cp|CN3005 equivalent}}, double DDR2 memory access, as well as support for TDM/PCM (VoIP support). | ||
+ | |||
+ | == Cache == | ||
+ | {{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=24 KiB | ||
+ | |l1i cache=16 KiB | ||
+ | |l1i break=1x16 KiB | ||
+ | |l1i desc=2-way set associative | ||
+ | |l1d cache=8 KiB | ||
+ | |l1d break=1x8 KiB | ||
+ | |l1d desc=64-way set associative | ||
+ | |l1d policy=Write-through | ||
+ | |l2 cache=128 KiB | ||
+ | |l2 break=1x128 KiB | ||
+ | |l2 desc=4-way set associative | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR2-533 | ||
+ | |ecc=Yes | ||
+ | |max mem=2 GiB | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=32 bit | ||
+ | |max bandwidth=1.986 MiB/s | ||
+ | |bandwidth schan=1.986 MiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |pci width=32 bit | ||
+ | |pci clock=66.66 MHz | ||
+ | |pci rate=254.31 MiB/s | ||
+ | |pci extra=host or slave | ||
+ | |usb revision=2.0 | ||
+ | |usb ports=1 | ||
+ | |usb rate=60 MB/s | ||
+ | |usb extra=host / PHY | ||
+ | |uart=yes | ||
+ | |uart ports=2 | ||
+ | |gp io=Yes | ||
+ | }} |
Revision as of 20:35, 8 December 2016
Template:mpu The CN3010-400 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 400 MHz and dissipates 3 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the CN3005 equivalent, double DDR2 memory access, as well as support for TDM/PCM (VoIP support).
Cache
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Facts about "CN3010-400 CP - Cavium"
base frequency | 400 MHz (0.4 GHz, 400,000 kHz) + |
core count | 1 + |
core name | cnMIPS + |
designer | Cavium + |
family | OCTEON + |
first announced | January 30, 2006 + |
first launched | May 1, 2006 + |
full page name | cavium/octeon/cn3010-400bg525-cp + |
has ecc memory support | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) + |
ldate | May 1, 2006 + |
main image | + |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory | 2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) + |
max memory bandwidth | 1.986 GiB/s (2,033.664 MiB/s, 2.132 GB/s, 2,132.451 MB/s, 0.00194 TiB/s, 0.00213 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN3010-400 CP + |
name | Cavium CN3010-400 CP + |
part number | CN3010-400BG525-CP + |
power dissipation | 3 W (3,000 mW, 0.00402 hp, 0.003 kW) + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
series | CN3000 + |
smp max ways | 1 + |
supported memory type | DDR2-533 + |
technology | CMOS + |
thread count | 1 + |
word size | 64 bit (8 octets, 16 nibbles) + |