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Difference between revisions of "cavium/octeon/cn3005-500bg350-cp"
< cavium‎ | octeon

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|l2 break=1x64 KiB
 
|l2 break=1x64 KiB
 
|l2 desc=2-way set associative
 
|l2 desc=2-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR2-533
 +
|ecc=No
 +
|max mem=2 GiB
 +
|controllers=1
 +
|channels=1
 +
|width=16 bit
 +
|max bandwidth=1,017 MiB/s
 +
|bandwidth schan=1,017 MiB/s
 
}}
 
}}

Revision as of 07:33, 8 December 2016

Template:mpu The CN3005-500 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2005. This processor, which incorporates a single cnMIPS core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$24 KiB
24,576 B
0.0234 MiB
L1I$16 KiB
16,384 B
0.0156 MiB
1x16 KiB2-way set associative 
L1D$8 KiB
8,192 B
0.00781 MiB
1x8 KiB64-way set associativeWrite-through
L2$64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
  1x64 KiB2-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-533
Supports ECCNo
Max Mem2 GiB
Controllers1
Channels1
Width16 bit
Max Bandwidth1,017 MiB/s
0.993 GiB/s
1.066 GB/s
1,066.402 MB/s
9.698868e-4 TiB/s
0.00107 TB/s
Bandwidth
Single 1,017 MiB/s
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3005-500bg350-cp&oldid=30655"
Facts about "CN3005-500 CP - Cavium"
RDF feed
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count1 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3005-500bg350-cp +
has ecc memory supportfalse +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size24 KiB (24,576 B, 0.0234 MiB) +
l1d$ description64-way set associative +
l1d$ size8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description2-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description2-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
ldateMay 1, 2006 +
main imageFile:cn3005-15.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3005-500 CP +
nameCavium CN3005-500 CP +
part numberCN3005-500BG350-CP +
power dissipation4 W (4,000 mW, 0.00536 hp, 0.004 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3000 +
smp max ways1 +
supported memory typeDDR2-533 +
technologyCMOS +
thread count1 +
word size64 bit (8 octets, 16 nibbles) +