Difference between revisions of "socionext/sc2a11"

Revision as of 04:10, 6 December 2016

Template:mpu SC2A11 is a 64-bit tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge computing. This chip, which incorporates 24 ultra-low power Cortex-A53 cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

1.5 MiB

1,536 KiB
1,572,864 B

L1I$	768 KiB 786,432 B 0.75 MiB	24x32 KiB	2-way set associative
L1D$	768 KiB 786,432 B 0.75 MiB	24x32 KiB	4-way set associative

L2$

1.5 MiB

1,536 KiB
1,572,864 B
0.00146 GiB

		2x256 KiB	16-way set associative

L3$

4 MiB

4,096 KiB
4,194,304 B
0.00391 GiB

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2133
Supports ECC	Yes
Channels	1
Max Bandwidth	15.89 GiB/s 16,271.36 MiB/s 17.062 GB/s 17,061.758 MB/s 0.0155 TiB/s 0.0171 TB/s
Bandwidth	Single 15.89 GiB/s

Expansions

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	2.0
Max Lanes	4

UART

GP I/O	Yes

Graphics

This SoC has no integrated graphics processing unit.

Networking

2x Gigabit Ethernet Interfaces

Storage

SPI
eMMC

@@ Line 19: / Line 19: @@
 | market 3            = IoT
 | first announced     = November 14, 2016
-| first launched      =
+| first launched      = 2017
 | last order          =
 | last shipment       =

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	SC2A11 - Socionext#io +
base frequency	1,000 MHz (1 GHz, 1,000,000 kHz) +
bus type	AMBA +
core count	24 +
core name	Cortex-A53 +
designer	Socionext + and ARM Holdings +
first announced	November 14, 2016 +
first launched	2017 +
full page name	socionext/sc2a11 +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8 +
isa family	ARM +
l1$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description	4-way set associative +
l1d$ size	768 KiB (786,432 B, 0.75 MiB) +
l1i$ description	2-way set associative +
l1i$ size	768 KiB (786,432 B, 0.75 MiB) +
l2$ description	16-way set associative +
l2$ size	3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate	3000 +
main image	+
market segment	Server +, Networking + and IoT +
max cpu count	64 +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels	2 +
max pcie lanes	4 +
microarchitecture	Cortex-A53 +
model number	SC2A11 +
name	Socionext SC2A11 +
smp max ways	64 +
supported memory type	DDR4-2133 +
tdp	5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
technology	CMOS +
thread count	24 +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas