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Difference between revisions of "intel/xeon e7/e7-2850"
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(→‎Cache)
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== Memory controller ==
 
== Memory controller ==
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{{integrated memory controller
+
{{memory controller
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| type               = DDR3-800
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|type=DDR3-1066
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| type 2            = DDR3-978
+
|ecc=Yes
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| type 3            = DDR3-1066
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|max mem=1 TiB
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| controllers       = 1
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|controllers=1
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| channels           = 4
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|channels=4
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| ecc support        = Yes
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|max bandwidth=31.77 GiB/s
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| max bandwidth     =  
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|bandwidth schan=7.942 GiB/s
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| bandwidth schan    =  
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|bandwidth dchan=15.88 GiB/s
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| bandwidth dchan    =  
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|bandwidth tchan=23.83 GiB/s
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| max memory        = 1024 GB
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|bandwidth qchan=31.77 GiB/s
 
}}
 
}}
  

Revision as of 02:03, 2 December 2016

Template:mpu Xeon E7-2850 is a 64-bit deca-core x86 data center microprocessor that supports up to 2 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2 GHz with turob frequency of 2.4 GHz for 2 active cores. This chip has a TDP of 130 W, supporting up to 4 channels of DDR3 with support of up to 1 TB of memory.

Cache

Main article: Westmere § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$640 KiB
655,360 B
0.625 MiB
L1I$320 KiB
327,680 B
0.313 MiB
10x32 KiB4-way set associativewrite-back
L1D$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associativewrite-back
L2$2.56 MiB
2,621.44 KiB
2,684,354.56 B
0.0025 GiB
  10x256 KiB8-way set associativewrite-back
L3$24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
  10x2.4 MiB16-way set associativewrite-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066
Supports ECCYes
Max Mem1 TiB
Controllers1
Channels4
Max Bandwidth31.77 GiB/s
32,532.48 MiB/s
34.113 GB/s
34,112.778 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 7.942 GiB/s
Double 15.88 GiB/s
Triple 23.83 GiB/s
Quad 31.77 GiB/s

Features

Template:mpu features

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Facts about "Xeon E7-2850 - Intel"
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has ecc memory supporttrue +
l1$ size640 KiB (655,360 B, 0.625 MiB) +
l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description4-way set associative +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ description8-way set associative +
l2$ size2.56 MiB (2,621.44 KiB, 2,684,354.56 B, 0.0025 GiB) +
l3$ description16-way set associative +
l3$ size24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
max memory bandwidth31.77 GiB/s (32,532.48 MiB/s, 34.113 GB/s, 34,112.778 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels4 +
supported memory typeDDR3-1066 +