Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon e7/e7-8830"
(→Cache) |
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| Line 24: | Line 24: | ||
| frequency = 2,133.33 MHz | | frequency = 2,133.33 MHz | ||
| turbo frequency = Yes | | turbo frequency = Yes | ||
| − | | turbo frequency1 = | + | | turbo frequency1 = 2,399.99 MHz |
| turbo frequency2 = 2,399.99 MHz | | turbo frequency2 = 2,399.99 MHz | ||
| − | | turbo frequency3 = | + | | turbo frequency3 = 2,266.66 MHz |
| turbo frequency4 = 2,266.66 MHz | | turbo frequency4 = 2,266.66 MHz | ||
| − | | turbo frequency5 = | + | | turbo frequency5 = 2,266.66 MHz |
| turbo frequency6 = 2,266.66 MHz | | turbo frequency6 = 2,266.66 MHz | ||
| − | | turbo frequency7 = | + | | turbo frequency7 = 2,266.66 MHz |
| turbo frequency8 = 2,266.66 MHz | | turbo frequency8 = 2,266.66 MHz | ||
| bus type = QPI | | bus type = QPI | ||
| Line 42: | Line 42: | ||
| microarch = Westmere | | microarch = Westmere | ||
| − | | platform = | + | | platform = Boxboro |
| chipset = Boxboro | | chipset = Boxboro | ||
| core name = Westmere EX | | core name = Westmere EX | ||
| Line 91: | Line 91: | ||
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | {{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | ||
| − | {{cache | + | {{cache size |
| + | |l1 cache=512 KiB | ||
|l1i cache=256 KiB | |l1i cache=256 KiB | ||
|l1i break=8x32 KiB | |l1i break=8x32 KiB | ||
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
| − | |l1i | + | |l1i policy=write-back |
|l1d cache=256 KiB | |l1d cache=256 KiB | ||
|l1d break=8x32 KiB | |l1d break=8x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
| − | |l1d | + | |l1d policy=write-back |
|l2 cache=2 MiB | |l2 cache=2 MiB | ||
|l2 break=8x256 KiB | |l2 break=8x256 KiB | ||
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
| − | |l2 | + | |l2 policy=write-back |
|l3 cache=24 MiB | |l3 cache=24 MiB | ||
| + | |l3 break=8x3 MiB | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
| + | |l3 policy=write-back | ||
}} | }} | ||
Revision as of 00:13, 2 December 2016
Template:mpu Xeon E7-8830 is a 64-bit octa-core x86 data center microprocessor that supports up to 8 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2.13 GHz with turob frequency of 2.4 GHz for 2 active cores. This chip has a TDP of 105 W, supporting up to 4 channels of DDR3 with support of up to 4 TB of memory.
Contents
Cache
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
This SoC has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR3-800, DDR3-978, DDR3-1066 |
| Controllers | 1 |
| Channels | 4 |
| ECC Support | Yes |
| Max memory | 4096 GB |
Features
Facts about "Xeon E7-8830 - Intel"
| l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |