Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i5/i5-520um"
| Line 94: | Line 94: | ||
|l3 desc=12-way set associative | |l3 desc=12-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
| + | }} | ||
| + | |||
| + | == Memory controller == | ||
| + | {{memory controller | ||
| + | |type=DDR3-800 | ||
| + | |ecc=No | ||
| + | |max mem=8 GiB | ||
| + | |controllers=1 | ||
| + | |channels=2 | ||
| + | |max bandwidth=11.92 GiB/s | ||
| + | |bandwidth schan=5.96 GiB/s | ||
| + | |bandwidth dchan=11.92 GiB/s | ||
| + | |pae=36 bit | ||
}} | }} | ||
Revision as of 06:56, 30 November 2016
Template:mpu Core i5-520UM is a 64-bit x86 dual-core mobile microprocessor introduced by Intel in 2010. This processor, which is based on the Westmere microarchitecture (Arrandale core), is manufactured on a 32 nm process. This MPU operates at a base frequency of 1.07 GHz with a Turbo Boost frequency of 1.87 GHz and a TDP of 18 W. This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 166.00 MHz and a burst frequency of 500.00 MHz.
Cache
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "Core i5-520UM - Intel"
| has ecc memory support | false + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 12-way set associative + |
| l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 2 + |
| supported memory type | DDR3-800 + |