Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i5/i5-520um"
| Line 32: | Line 32: | ||
| s-spec 2 = SLBSQ | | s-spec 2 = SLBSQ | ||
| s-spec qs = | | s-spec qs = | ||
| − | | cpuid = | + | | cpuid = 0x20655 |
| microarch = Westmere | | microarch = Westmere | ||
| Line 53: | Line 53: | ||
| max cpus = 1 | | max cpus = 1 | ||
| max memory = 8 GiB | | max memory = 8 GiB | ||
| + | |||
| + | | electrical = Yes | ||
| + | | v core = | ||
| + | | v core tolerance = | ||
| + | | v io = | ||
| + | | v io tolerance = | ||
| + | | sdp = | ||
| + | | tdp = 18 W | ||
| + | | tjunc min = 0 °C | ||
| + | | tjunc max = 105 °C | ||
| + | | tcase min = | ||
| + | | tcase max = | ||
| + | | tstorage min = -25 °C | ||
| + | | tstorage max = 125 °C | ||
| + | | tambient min = | ||
| + | | tambient max = | ||
| + | |||
| + | | package module 1 = {{packages/intel/bga-1288}} | ||
}} | }} | ||
'''Core i5-520UM''' is a {{arch|64}} [[x86]] [[dual-core]] mobile microprocessor introduced by [[Intel]] in [[2010]]. This processor, which is based on the {{intel|Westmere|l=arch}} microarchitecture ({{intel|Arrandale|l=core}} core), is manufactured on a [[32 nm process]]. This MPU operates at a base frequency of 1.07 GHz with a {{intel|Turbo Boost}} frequency of 1.87 GHz and a TDP of 18 W. This processor incorporated the {{intel|HD Graphics (Ironlake)}} [[IGP]] on the same package operating at a base frequency of 166.00 MHz and a burst frequency of 500.00 MHz. | '''Core i5-520UM''' is a {{arch|64}} [[x86]] [[dual-core]] mobile microprocessor introduced by [[Intel]] in [[2010]]. This processor, which is based on the {{intel|Westmere|l=arch}} microarchitecture ({{intel|Arrandale|l=core}} core), is manufactured on a [[32 nm process]]. This MPU operates at a base frequency of 1.07 GHz with a {{intel|Turbo Boost}} frequency of 1.87 GHz and a TDP of 18 W. This processor incorporated the {{intel|HD Graphics (Ironlake)}} [[IGP]] on the same package operating at a base frequency of 166.00 MHz and a burst frequency of 500.00 MHz. | ||
Revision as of 06:35, 30 November 2016
Template:mpu Core i5-520UM is a 64-bit x86 dual-core mobile microprocessor introduced by Intel in 2010. This processor, which is based on the Westmere microarchitecture (Arrandale core), is manufactured on a 32 nm process. This MPU operates at a base frequency of 1.07 GHz with a Turbo Boost frequency of 1.87 GHz and a TDP of 18 W. This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 166.00 MHz and a burst frequency of 500.00 MHz.