Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i7/i7-680um"
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| − | '''Core i7-680UM''' is a {{arch|64}} [[dual-core]] [[x86-64]] mobile microprocessor designed by [[Intel]] and introduced in early [[2010]]. This chip is a first-generation {{intel|Core i7}} processor based on the {{intel|Westmere|l=arch}} microarchitecture and is manufactured on a [[32 nm process]]. This processor operated at a based frequency of 1.46 GHz with a {{intel|Turbo Boost Technology|turbo frequency}} of 2.53 GHz and a TDP of 18 W. This MPU came with a {{intel|HD Graphics (Ironlake)}} [[IGP]] operating at 166 MHz with a max burst frequency of 500 MHz. | + | '''Core i7-680UM''' is a {{arch|64}} [[dual-core]] [[x86-64]] mobile microprocessor designed by [[Intel]] and introduced in early [[2010]]. This chip is a first-generation {{intel|Core i7}} processor based on the {{intel|Westmere|l=arch}} microarchitecture and is manufactured on a [[32 nm process]]. This processor operated at a based frequency of 1.46 GHz with a {{intel|Turbo Boost Technology|turbo frequency}} of 2.53 GHz and a TDP of 18 W. This MPU came with a {{intel|HD Graphics (Ironlake)}} [[IGP]] operating at 166 MHz with a max burst frequency of 500 MHz. This model is part of the [[part of::Ultra-Low Power]] series. |
== Cache == | == Cache == | ||
Revision as of 18:11, 28 November 2016
Template:mpu Core i7-680UM is a 64-bit dual-core x86-64 mobile microprocessor designed by Intel and introduced in early 2010. This chip is a first-generation Core i7 processor based on the Westmere microarchitecture and is manufactured on a 32 nm process. This processor operated at a based frequency of 1.46 GHz with a turbo frequency of 2.53 GHz and a TDP of 18 W. This MPU came with a HD Graphics (Ironlake) IGP operating at 166 MHz with a max burst frequency of 500 MHz. This model is part of the Ultra-Low Power series.
Cache
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Core i7-680UM - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i7-680UM - Intel#io + |
| device id | 0x0046 + |
| has ecc memory support | false + |
| has extended page tables support | true + |
| has feature | Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 1.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Flex Memory Access + |
| has intel enhanced speedstep technology | true + |
| has intel flex memory access support | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 1 0 | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| integrated gpu | HD Graphics (Ironlake) + |
| integrated gpu base frequency | 166 MHz (0.166 GHz, 166,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 12 + |
| integrated gpu max frequency | 500 MHz (0.5 GHz, 500,000 KHz) + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| part of | Ultra-Low Power + |
| supported memory type | DDR3-800 + |