From WikiChip
Difference between revisions of "intel/core i7/i7-660lm"
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| pcie lanes = 16 | | pcie lanes = 16 | ||
| pcie config = 1x16 | | pcie config = 1x16 | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=No | ||
+ | |avx2=No | ||
+ | |avx512=No | ||
+ | |abm=No | ||
+ | |tbm=No | ||
+ | |bmi1=No | ||
+ | |bmi2=No | ||
+ | |fma3=No | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=No | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=No | ||
+ | |clmul=No | ||
+ | |f16c=No | ||
+ | |tbt1=Yes | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |flex=Yes | ||
+ | |fastmem=Yes | ||
+ | |isrt=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdv=No | ||
+ | |rvi=No | ||
}} | }} |
Revision as of 17:01, 27 November 2016
Template:mpu Core i7-660LM is a 64-bit dual-core x86-64 mobile microprocessor designed by Intel and introduced in early 2010. This chip is a first-generation Core i7 processor based on the Westmere microarchitecture and is manufactured on a 32 nm process. This processor operated at a based frequency of 2.26 GHz with a turbo frequency of 3.06 GHz and a TDP of 25 W. This MPU came with a HD Graphics (Ironlake) IGP operating at 266 MHz with a max burst frequency of 566 MHz.
Contents
Cache
- Main article: Westmere § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "Core i7-660LM - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i7-660LM - Intel#io + |
has ecc memory support | false + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
max memory bandwidth | 15.88 GiB/s (16,261.12 MiB/s, 17.051 GB/s, 17,051.02 MB/s, 0.0155 TiB/s, 0.0171 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
supported memory type | DDR3-1066 + |