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Difference between revisions of "intel/core i3/i3-7310t"
< intel‎ | core i3

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{{unknown features}}
 
{{unknown features}}
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== Cache ==
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{{main|intel/microarchitectures/kaby lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
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{{cache info
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|l1i cache=64 KiB
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|l1i break=2x32 KiB
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|l1i desc=8-way set associative
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|l1i extra=(per core, write-back)
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|l1d cache=64 KiB
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|l1d break=2x32 KiB
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|l1d desc=8-way set associative
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|l1d extra=(per core, write-back)
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|l2 cache=512 KiB
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|l2 break=2x256 KiB
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|l2 desc=4-way set associative
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|l2 extra=(per core, write-back)
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|l3 cache=3 MiB
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|l3 desc=shared
 +
}}

Revision as of 23:44, 5 November 2016

Template:mpu The Core i3-7310t is a 64-bit dual-core x86 low-end microprocessor set to be introduced by Intel in late 2016 or early 2017. This processor operates at 3.4 GHz with a TDP of 35 W


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Kaby Lake § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L1D$ 64 KiB
65,536 B
0.0625 MiB
2x32 KiB 8-way set associative (per core, write-back)
L2$ 512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
2x256 KiB 4-way set associative (per core, write-back)
L3$ 3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
shared
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i3/i3-7310t&oldid=27166"
Facts about "Core i3-7310T - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description4-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ descriptionshared +
l3$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +