From WikiChip
Difference between revisions of "intel/xeon e3/e3-1245 v6"
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| s-spec qs = | | s-spec qs = | ||
| cpuid = | | cpuid = | ||
+ | |||
+ | | microarch = Kaby Lake | ||
+ | | platform = | ||
+ | | chipset = | ||
+ | | core name = | ||
+ | | core family = | ||
+ | | core model = | ||
+ | | core stepping = | ||
+ | | process = 14 nm | ||
+ | | transistors = | ||
+ | | technology = CMOS | ||
+ | | die size = | ||
+ | | word size = 64 bit | ||
+ | | core count = 4 | ||
+ | | thread count = 8 | ||
+ | | max cpus = 1 | ||
+ | | max memory = | ||
| electrical = | | electrical = |
Revision as of 00:16, 6 November 2016
Template:mpu The Xeon E3-1245 v6 is a 64-bit quad-core x86 microprocessor set to be introduced by Intel in late 2016 or early 2017. Operating at 3.7 GHz, this MPU has a TDP of 78 W. This processor is a Kaby Lake-based chip and is manufactured on a Intel's 14 nm process.
Facts about "Xeon E3-1245 v6 - Intel"
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | shared + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |