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Difference between revisions of "intel/xeon e5/e5-2650 v4"
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| s-spec qs          =  
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| s-spec qs          = QK8Y
 
| cpuid              = 406F1
 
| cpuid              = 406F1
  

Revision as of 00:40, 5 November 2016

Template:mpu The Xeon E5-2650 v4 is a 64-bit dodeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for advanced 2S environments (1U square form factor). Operating at 2.2 GHz with a turbo boost frequency of 2.9 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 384 KiB
393,216 B
0.375 MiB
12x32 KiB 8-way set associative (per core, write-back)
L1D$ 384 KiB
393,216 B
0.375 MiB
12x32 KiB 8-way set associative (per core, write-back)
L2$ 3 MiB
3,072 KiB
3,145,728 B
0.00293 GiB
12x256 KiB 8-way set associative (per core, write-back)
L3$ 30 MiB
30,720 KiB
31,457,280 B
0.0293 GiB
12x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2650_v4&oldid=26951"
Facts about "Xeon E5-2650 v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description8-way set associative +
l2$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ description20-way set associative +
l3$ size30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) +