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Difference between revisions of "intel/xeon e5/e5-2618l v4"
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+ | }} | ||
+ | The '''Xeon E5-2618L v4''' is a {{arch|64}} [[deca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for low-power 2S environments (1U square form factor). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 75 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}} | ||
+ | {{cache info | ||
+ | |l1i cache=320 KiB | ||
+ | |l1i break=10x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1i extra=(per core, write-back) | ||
+ | |l1d cache=320 KiB | ||
+ | |l1d break=10x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d extra=(per core, write-back) | ||
+ | |l2 cache=2.5 MiB | ||
+ | |l2 break=10x256 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 extra=(per core, write-back) | ||
+ | |l3 cache=25 MiB | ||
+ | |l3 break=10x2.5 MiB | ||
+ | |l3 desc=20-way set associative | ||
+ | |l3 extra=(shared, per core, write-back) | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | This microprocessor has no [[integrated graphics processing unit]]. | ||
+ | |||
+ | == Memory controller == | ||
+ | {{integrated memory controller | ||
+ | | type = DDR4-2133 | ||
+ | | controllers = 1 | ||
+ | | channels = 4 | ||
+ | | ecc support = Yes | ||
+ | | max bandwidth = 63.58 GiB/s | ||
+ | | bandwidth schan = 15.89 GiB/s | ||
+ | | bandwidth dchan = 31.79 GiB/s | ||
+ | | max memory = 1,536 GiB | ||
+ | | pae = 46 bit | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{mpu expansions | ||
+ | | pcie revision = 3.0 | ||
+ | | pcie lanes = 40 | ||
+ | | pcie config = x4 | ||
+ | | pcie config 1 = x8 | ||
+ | | pcie config 2 = x16 | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{mpu features | ||
+ | | em64t = Yes | ||
+ | | nx = Yes | ||
+ | | txt = Yes | ||
+ | | tsx = Yes | ||
+ | | vpro = Yes | ||
+ | | ht = Yes | ||
+ | | tbt1 = | ||
+ | | tbt2 = Yes | ||
+ | | tbmt3 = | ||
+ | | bpt = | ||
+ | | vt-x = Yes | ||
+ | | vt-d = Yes | ||
+ | | ept = Yes | ||
+ | | mmx = Yes | ||
+ | | sse = Yes | ||
+ | | sse2 = Yes | ||
+ | | sse3 = Yes | ||
+ | | ssse3 = Yes | ||
+ | | sse4.1 = Yes | ||
+ | | sse4.2 = Yes | ||
+ | | aes = Yes | ||
+ | | pclmul = Yes | ||
+ | | avx = Yes | ||
+ | | avx2 = Yes | ||
+ | | bmi = Yes | ||
+ | | bmi1 = Yes | ||
+ | | bmi2 = Yes | ||
+ | | f16c = Yes | ||
+ | | fma3 = Yes | ||
+ | | mpx = | ||
+ | | sgx = | ||
+ | | eist = Yes | ||
+ | | secure key = Yes | ||
+ | | os guard = Yes | ||
+ | | intel at = | ||
+ | | intel ipt = | ||
}} | }} |
Revision as of 23:23, 4 November 2016
Template:mpu The Xeon E5-2618L v4 is a 64-bit deca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for low-power 2S environments (1U square form factor). Operating at 2.2 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 75 W and is manufactured on a 14 nm process (based on Broadwell).
Cache
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 320 KiB 327,680 B 0.313 MiB |
10x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 320 KiB 327,680 B 0.313 MiB |
10x32 KiB 8-way set associative (per core, write-back) |
L2$ | 2.5 MiB 2,560 KiB 2,621,440 B 0.00244 GiB |
10x256 KiB 8-way set associative (per core, write-back) |
L3$ | 25 MiB 25,600 KiB 26,214,400 B 0.0244 GiB |
10x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics
This microprocessor has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR4-2133 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max bandwidth | 63.58 GiB/s |
Bandwidth (single) | 15.89 GiB/s |
Bandwidth (dual) | 31.79 GiB/s |
Max memory | 1,536 GiB |
Physical Address Extensions | 46 bit |
Expansions
Features
Facts about "Xeon E5-2618L v4 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E5-2618L v4 - Intel#io + |
base frequency | 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
bus links | 2 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus speed | 4,000 MHz (4 GHz, 4,000,000 kHz) + |
bus type | QPI + |
chipset | C610 Series + |
clock multiplier | 22 + |
core count | 10 + |
core family | 6 + |
core model | 4F + |
core name | Broadwell EP + |
core stepping | R0 + |
core voltage | 1.82 V (18.2 dV, 182 cV, 1,820 mV) + |
cpuid | 406F1 + |
designer | Intel + |
die area | 246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) + |
family | Xeon E5 + |
first announced | June 20, 2016 + |
first launched | June 20, 2016 + |
full page name | intel/xeon e5/e5-2618l v4 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel vPro Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 + |
has intel enhanced speedstep technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
io voltage | 1.2 V (12 dV, 120 cV, 1,200 mV) + |
io voltage tolerance | 3% + |
isa | x86-64 + |
isa family | x86 + |
l1d$ description | 8-way set associative + |
l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) + |
ldate | June 20, 2016 + |
manufacturer | Intel + |
market segment | Embedded + |
max case temperature | 360.15 K (87 °C, 188.6 °F, 648.27 °R) + |
max cpu count | 2 + |
max memory | 1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) + |
max pcie lanes | 40 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Broadwell + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | E5-2618L v4 + |
name | Xeon E5-2618L v4 + |
part number | CM8066002061300 + |
platform | Grantley EP 2S + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 779.00 (€ 701.10, £ 630.99, ¥ 80,494.07) + |
s-spec | SR2PE + |
series | E5-2000 + |
smp max ways | 2 + |
tdp | 75 W (75,000 mW, 0.101 hp, 0.075 kW) + |
technology | CMOS + |
thread count | 20 + |
transistor count | 3,200,000,000 + |
turbo frequency (10 cores) | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
turbo frequency (1 core) | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
turbo frequency (2 cores) | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
turbo frequency (3 cores) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
turbo frequency (4 cores) | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
turbo frequency (5 cores) | 2,800 MHz (2.8 GHz, 2,800,000 kHz) + |
turbo frequency (6 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (7 cores) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
turbo frequency (8 cores) | 2,500 MHz (2.5 GHz, 2,500,000 kHz) + |
turbo frequency (9 cores) | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |