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Difference between revisions of "intel/xeon e5/e5-2687w v4"
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The '''Xeon E5-2687W v4''' is a {{arch|64}} [[dodeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for 2S workstation environments. Operating at 3 GHz with a {{intel|turbo boost}} frequency of 3.5 GHz for a single active core, this MPU has a TDP of 160 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). | The '''Xeon E5-2687W v4''' is a {{arch|64}} [[dodeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for 2S workstation environments. Operating at 3 GHz with a {{intel|turbo boost}} frequency of 3.5 GHz for a single active core, this MPU has a TDP of 160 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}). | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}} | ||
+ | {{cache info | ||
+ | |l1i cache=384 KiB | ||
+ | |l1i break=12x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1i extra=(per core, write-back) | ||
+ | |l1d cache=384 KiB | ||
+ | |l1d break=12x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d extra=(per core, write-back) | ||
+ | |l2 cache=3 MiB | ||
+ | |l2 break=12x256 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 extra=(per core, write-back) | ||
+ | |l3 cache=30 MiB | ||
+ | |l3 break=12x2.5 MiB | ||
+ | |l3 desc=20-way set associative | ||
+ | |l3 extra=(shared, per core, write-back) | ||
+ | }} |
Revision as of 11:05, 3 November 2016
Template:mpu The Xeon E5-2687W v4 is a 64-bit dodeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 2S workstation environments. Operating at 3 GHz with a turbo boost frequency of 3.5 GHz for a single active core, this MPU has a TDP of 160 W and is manufactured on a 14 nm process (based on Broadwell).
Cache
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 384 KiB 393,216 B 0.375 MiB |
12x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 384 KiB 393,216 B 0.375 MiB |
12x32 KiB 8-way set associative (per core, write-back) |
L2$ | 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB |
12x256 KiB 8-way set associative (per core, write-back) |
L3$ | 30 MiB 30,720 KiB 31,457,280 B 0.0293 GiB |
12x2.5 MiB 20-way set associative (shared, per core, write-back) |
Facts about "Xeon E5-2687W v4 - Intel"
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) + |