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Difference between revisions of "amd/duron/dhm0800avs1bm"
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The '''Mobile Duron 800''' based on the {{amd|Morgan|l=core}} (Camaro) core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2001. This model was part of the second generation of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} on a [[180 nm process]], this MPU operated at 800 MHz with a bus capable of 200 MT/s.
 
The '''Mobile Duron 800''' based on the {{amd|Morgan|l=core}} (Camaro) core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2001. This model was part of the second generation of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} on a [[180 nm process]], this MPU operated at 800 MHz with a bus capable of 200 MT/s.
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== Cache ==
 +
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
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{{cache info
 +
|l1i cache=64 KiB
 +
|l1i break=1x64 KiB
 +
|l1i desc=2-way set associative
 +
|l1i extra=
 +
|l1d cache=64 KiB
 +
|l1d break=1x64 KiB
 +
|l1d desc=2-way set associative
 +
|l1d extra=
 +
|l2 cache=64 KiB
 +
|l2 break=1x64 KiB
 +
|l2 desc=16-way set associative
 +
|l2 extra=
 +
|l3 cache=
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|l3 break=
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|l3 desc=
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|l3 extra=
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}}
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 +
== Graphics ==
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This SoC has no integrated graphics processing unit.
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 +
== Features ==
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{{mpu features
 +
| em64t      =
 +
| nx          =
 +
| txt        =
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| tsx        =
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| vpro        =
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| ht          =
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| tbt1        =
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| tbt2        =
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| bpt        =
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| vt-x        =
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| vt-d        =
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| ept        =
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| mmx        = Yes
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| emmx        = Yes
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| 3dnow      = Yes
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| e3dnow      = Yes
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| sse        = Yes
 +
| sse2        =
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| sse3        =
 +
| ssse3      =
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| sse4        =
 +
| sse4.1      =
 +
| sse4.2      =
 +
| aes        =
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| pclmul      =
 +
| avx        =
 +
| avx2        =
 +
| bmi        =
 +
| bmi1        =
 +
| bmi2        =
 +
| f16c        =
 +
| fma3        =
 +
| mpx        =
 +
| sgx        =
 +
| eist        =
 +
}}
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* [[has feature::Halt State]]
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* [[has feature::Sleep State]]
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== See also ==
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* {{amd|Duron}}
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* {{intel|Celeron}}

Revision as of 15:37, 24 October 2016

Template:mpu The Mobile Duron 800 based on the Morgan (Camaro) core was a 32-bit x86 microprocessor developed by AMD and introduced in 2001. This model was part of the second generation of the Duron family. Designed based on AMD's K7 on a 180 nm process, this MPU operated at 800 MHz with a bus capable of 200 MT/s.

Cache

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB 16-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Halt State
  • Sleep State

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/duron/dhm0800avs1bm&oldid=26134"
Facts about "Duron 800 (Camaro) - AMD"
RDF feed
has featureHalt State + and Sleep State +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +