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The '''Mobile Pentium II 400''' is a {{arch|32}} [[x86]] microprocessor, part of the {{intel|Mobile Pentium II}} family, which operated at 400 MHz. This was the Pentium II Mobile family's highest performance processor. This processor had a TDP of 13.1 Watts. This chip was manufactured in [[250 nm process]] and includes a smaller 256 KB of [[L2$]] on-die. This is the only processor in the family to later be manufactured in [[180 nm]].
 
The '''Mobile Pentium II 400''' is a {{arch|32}} [[x86]] microprocessor, part of the {{intel|Mobile Pentium II}} family, which operated at 400 MHz. This was the Pentium II Mobile family's highest performance processor. This processor had a TDP of 13.1 Watts. This chip was manufactured in [[250 nm process]] and includes a smaller 256 KB of [[L2$]] on-die. This is the only processor in the family to later be manufactured in [[180 nm]].
 
== Cache ==
 
== Cache ==
{{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6's Cache}}
+
{{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6 § Cache}}
 
{{cache info
 
{{cache info
|l1i cache=16 KB
+
|l1i cache=16 KiB
|l1i break=1x16 KB
+
|l1i break=1x16 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
 
|l1i extra=
 
|l1i extra=
|l1d cache=16 KB
+
|l1d cache=16 KiB
|l1d break=1x16 KB
+
|l1d break=1x16 KiB
 
|l1d desc=4-way set associative
 
|l1d desc=4-way set associative
 
|l1d extra=
 
|l1d extra=
|l2 cache=256 KB
+
|l2 cache=256 KiB
|l2 break=1x256 KB
+
|l2 break=1x256 KiB
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
 
|l2 extra=(on-die)
 
|l2 extra=(on-die)

Revision as of 23:59, 20 September 2016

Template:mpu The Mobile Pentium II 400 is a 32-bit x86 microprocessor, part of the Mobile Pentium II family, which operated at 400 MHz. This was the Pentium II Mobile family's highest performance processor. This processor had a TDP of 13.1 Watts. This chip was manufactured in 250 nm process and includes a smaller 256 KB of L2$ on-die. This is the only processor in the family to later be manufactured in 180 nm.

Cache

Main article: P6 § Cache
Cache Info [Edit Values]
L1I$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 4-way set associative
L1D$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 4-way set associative
L2$ 256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
1x256 KiB 4-way set associative (on-die)

Graphics

This processor has no integrated graphics processing unit.

Memory controller

This processor has no integrated memory controller.

Features

Template:mpu features

l1d$ description4-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description4-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +