Semiconductor & Computer Engineering
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Difference between revisions of "intel/mobile pentium ii/233"
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== Cache == | == Cache == | ||
| − | {{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6 | + | {{main|intel/microarchitectures/p6#Memory_Hierarchy|l1=P6 § Cache}} |
{{cache info | {{cache info | ||
| − | |l1i cache=16 | + | |l1i cache=16 KiB |
| − | |l1i break=1x16 | + | |l1i break=1x16 KiB |
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=16 | + | |l1d cache=16 KiB |
| − | |l1d break=1x16 | + | |l1d break=1x16 KiB |
|l1d desc=4-way set associative | |l1d desc=4-way set associative | ||
|l1d extra= | |l1d extra= | ||
| − | |l2 cache=512 | + | |l2 cache=512 KiB |
| − | |l2 break=1x512 | + | |l2 break=1x512 KiB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
|l2 extra=(separate die, same package) | |l2 extra=(separate die, same package) | ||
Revision as of 23:57, 20 September 2016
Template:mpu The Mobile Pentium II 233 was a 32-bit x86 microprocessor, the first of the Mobile Pentium II family. This processor operated at 233 MHz and had a TDP of 9 Watts. This chip was manufactured in 250 nm process and included a larger 512 KB of L2$ on package, but on a separate die.
Contents
Cache
- Main article: P6 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L1D$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB |
1x512 KiB 4-way set associative (separate die, same package) |
Graphics
This processor has no integrated graphics processing unit.
Memory controller
This processor has no integrated memory controller.
Features
Facts about "Mobile Pentium II 233 - Intel"
| base frequency | 233 MHz (0.233 GHz, 233,000 kHz) + |
| bus speed | 66 MHz (0.066 GHz, 66,000 kHz) + |
| bus type | FSB + |
| clock multiplier | 3.5 + |
| core count | 1 + |
| core family | 6 + |
| core model | 5 + |
| core name | Tonga + |
| core stepping | mdA0 + and mdB0 + |
| core voltage | 1.6 V (16 dV, 160 cV, 1,600 mV) + |
| core voltage tolerance | 0.12 V + |
| cpuid | 0650h + and 0652h + |
| designer | Intel + |
| die area | 131 mm² (0.203 in², 1.31 cm², 131,000,000 µm²) + |
| family | Mobile Pentium II + |
| first announced | May 1997 + |
| first launched | April 2, 1998 + |
| full page name | intel/mobile pentium ii/233 + |
| has locked clock multiplier | true + |
| instance of | microprocessor + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| ldate | April 2, 1998 + |
| manufacturer | Intel + |
| market segment | Mobile + |
| max cpu count | 1 + |
| max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
| max operating temperature | 85 °C + |
| microarchitecture | P6 + |
| min operating temperature | -40 °C + |
| model number | 233 + |
| name | Mobile Pentium II 233 + |
| part number | 80523TX233512 +, PMD23305002AB +, PME23305001AA + and PMD23305001AA + |
| process | 250 nm (0.25 μm, 2.5e-4 mm) + |
| s-spec | SL2KH +, SL2RQ + and SL2U8 + |
| smp max ways | 1 + |
| tdp | 9 W (9,000 mW, 0.0121 hp, 0.009 kW) + |
| technology | CMOS + |
| thread count | 1 + |
| transistor count | 7,500,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |