Difference between revisions of "intel/xeon e3/e3-1235l v5"

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Revision as of 23:11, 20 September 2016

Template:mpu The Xeon E3-1235L V5 is an entry-level workstations and servers 64-bit x86 quad-core microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 2 GHz with turbo boost of 3 GHz. The E3-1235L V5 is a special low-power chip with a TDP of 25 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has the HD Graphics P530 IGP.

1 Cache
2 Graphics
3 Memory controller
4 Expansions
5 Features

Cache

Main article: Skylake § Cache

Cache Info [Edit Values]
L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB 8-way set associative (per core, write-back)
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB 8-way set associative (per core, write-back)
L2$	1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB	4x256 KiB 4-way set associative (per core)
L3$	8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB	4x2 MiB

Graphics

Integrated Graphic Information
GPU	Intel HD Graphics P530
Device ID	0x191D
Execution Units	24
Displays	3
Frequency	400 MHz 0.4 GHz 400,000 KHz
Max frequency	1.15 GHz 1,150 MHz 1,150,000 KHz
Max memory	1.7 GB "GB" is not declared as a valid unit of measurement for this property.
Output	DisplayPort, Embedded DisplayPort, HDMI, DVI
DirectX	12.1
OpenGL	4.4
OpenCL	2.0
HDMI	1.4
DP	1.2
eDP	1.3
Max HDMI Res	4096x2160 @24 Hz
Max DP Res	4096x2304 @60 Hz
Max eDP Res	4096x2304 @60 Hz
	Intel Quick Sync Video
	Intel InTru 3D
	Intel Insider
	Intel WiDi (Wireless Display)
	Intel Clear Video

Memory controller

Integrated Memory Controller
Type	DDR3L-1333, DDR3L-1600, DDR3L-RS1333, DDR3L-RS1600, DDR4-1866, DDR4-2133, DDR4-RS1866, DDR4-RS2133
Controllers	1
Channels	2
ECC Support	Yes
Max bandwidth	34.1 GB/s
Max memory	64 GB

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e3/e3-1235l_v5&oldid=25670"

Facts about "Xeon E3-1235L v5 - Intel"

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Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon E3-1235L v5 - Intel#package + and Xeon E3-1235L v5 - Intel#io +
base frequency	2,000 MHz (2 GHz, 2,000,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Sunrise Point +
clock multiplier	20 +
core count	4 +
core family	6 +
core model	94 +
core name	Skylake DT +
core stepping	R0 +
core voltage (max)	1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)	0.55 V (5.5 dV, 55 cV, 550 mV) +
cpuid	506E3 +
designer	Intel +
device id	0x191D +
die area	122 mm² (0.189 in², 1.22 cm², 122,000,000 µm²) +
family	Xeon E3 +
first announced	October 19, 2015 +
first launched	October 19, 2015 +
full page name	intel/xeon e3/e3-1235l v5 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology + and OS Guard +
has intel enhanced speedstep technology	true +
has intel secure key technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	HD Graphics P530 +
integrated gpu base frequency	400 MHz (0.4 GHz, 400,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	24 +
integrated gpu max frequency	1,150 MHz (1.15 GHz, 1,150,000 KHz) +
integrated gpu max memory	1,740.8 MiB (1,782,579.2 KiB, 1,825,361,100.8 B, 1.7 GiB) +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	4-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldate	October 19, 2015 +
main image	+
manufacturer	Intel +
market segment	Server +
max cpu count	1 +
max junction temperature	373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels	2 +
max pcie lanes	16 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Skylake +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	E3-1235L v5 +
name	Xeon E3-1235L v5 +
package	FCLGA-1151 +
part number	CM8066201935807 +
platform	Greenlow +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 250.00 (€ 225.00, £ 202.50, ¥ 25,832.50) +
s-spec	SR2CV + and SR2LM +
series	E3-1200 v5 +
smp max ways	1 +
socket	LGA-1151 +
supported memory type	DDR3L-1600 + and DDR4-2133 +
tdp	25 W (25,000 mW, 0.0335 hp, 0.025 kW) +
technology	CMOS +
thread count	4 +
turbo frequency (1 core)	3,000 MHz (3 GHz, 3,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +
x86/has software guard extensions	true +

@@ Line 76: / Line 76: @@
 {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 {{cache info
-|l1i cache=128 KB
+|l1i cache=128 KiB
-|l1i break=4x32 KB
+|l1i break=4x32 KiB
 |l1i desc=8-way set associative
 |l1i extra=(per core, write-back)
-|l1d cache=128 KB
+|l1d cache=128 KiB
-|l1d break=4x32 KB
+|l1d break=4x32 KiB
 |l1d desc=8-way set associative
 |l1d extra=(per core, write-back)
-|l2 cache=1 MB
+|l2 cache=1 MiB
-|l2 break=4x256 KB
+|l2 break=4x256 KiB
 |l2 desc=4-way set associative
 |l2 extra=(per core)
@@ Line 91: / Line 91: @@
 |l3 break=4x2 MiB
 }}
 == Graphics ==
 {{integrated graphic

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