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Difference between revisions of "intrinsity/fastmath/fastmath-lp"
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{{main|intrinsity/microarchitectures/fastmath#Memory_Hierarchy|l1=FastMATH § Cache}} | {{main|intrinsity/microarchitectures/fastmath#Memory_Hierarchy|l1=FastMATH § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1i cache=16 | + | |l1i cache=16 KiB |
| − | |l1i break=1x16 | + | |l1i break=1x16 KiB |
|l1i desc=256 blocks × 16 words/block | |l1i desc=256 blocks × 16 words/block | ||
| − | + | |l1d cache=16 KiB | |
| − | |l1d cache=16 | + | |l1d break=1x16 KiB |
| − | |l1d break=1x16 | ||
|l1d desc=256 blocks × 16 words/block | |l1d desc=256 blocks × 16 words/block | ||
|l1d extra=write-through or write-back mode | |l1d extra=write-through or write-back mode | ||
| − | |l2 cache=1 | + | |l2 cache=1 MiB |
| − | |l2 break=1x1 | + | |l2 break=1x1 MiB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
| − | |l2 extra=(configurable as SRAM in 256 | + | |l2 extra=(configurable as SRAM in 256 KiB increments) |
| − | |||
| − | |||
| − | |||
| − | |||
}} | }} | ||
Revision as of 22:51, 20 September 2016
Template:mpu The FastMATH-LP was a microprocessor developed by Intrinsity operating at 1 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.
Contents
Cache
- Main article: FastMATH § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 256 blocks × 16 words/block |
| L1D$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 256 blocks × 16 words/block write-through or write-back mode |
| L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB |
1x1 MiB 4-way set associative (configurable as SRAM in 256 KiB increments) |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR-400 |
| Controllers | 1 |
| Channels | 2 |
| Max memory | 1 GB |
Matrix and Vector Unit
- SIMD architecture
- Operates on 4x4 array of 32-bit elements
- Fixed-point matrix, vector, and scalar data types
Features
- JTAG interface
- 8-bit or 32-bit wide bus operates up to 66 MHz
Documents
Manuals
Facts about "FastMATH-LP - Intrinsity"
| has feature | JTAG + |
| l1d$ description | 256 blocks × 16 words/block + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 256 blocks × 16 words/block + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |