Semiconductor & Computer Engineering
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Difference between revisions of "amd/k6-iii+/amd-k6-iiie+-400icr"
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== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k6-iii#Memory_Hierarchy|l1=K6-III § Cache}} | {{main|amd/microarchitectures/k6-iii#Memory_Hierarchy|l1=K6-III § Cache}} | ||
| − | [[L3$]] can be 512 | + | [[L3$]] can be 512 KiB to 2 MiB, depending on manufacturer and [[motherboard]] model. L3$ is off-chip. |
{{cache info | {{cache info | ||
| − | |l1i cache=32 | + | |l1i cache=32 KiB |
| − | |l1i break=1x32 | + | |l1i break=1x32 KiB |
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=32 | + | |l1d cache=32 KiB |
| − | |l1d break=1x32 | + | |l1d break=1x32 KiB |
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
|l1d extra= | |l1d extra= | ||
| − | |l2 cache=256 | + | |l2 cache=256 KiB |
| − | |l2 break=1x256 | + | |l2 break=1x256 KiB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
|l2 extra=(shared) | |l2 extra=(shared) | ||
Revision as of 22:08, 20 September 2016
Template:mpu AMD-K6-IIIE+/400ICR is a 32-bit x86 embedded microprocessor designed by AMD and introduced in late 2000. This MPU which was manufactured on a 0.18 µm process, based on K6-III microarchitecture, operated at 400 MHz with a bus of 100 MHz and a multiplier of 4. This chip had a TDP of 9.5 W.
Cache
- Main article: K6-III § Cache
L3$ can be 512 KiB to 2 MiB, depending on manufacturer and motherboard model. L3$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L2$ | 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB |
1x256 KiB 4-way set associative (shared) |
Graphics
This processors has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
- Halt state
Facts about "AMD-K6-IIIE+/400ICR - AMD"
| base frequency | 399.99 MHz (0.4 GHz, 399,990 kHz) + |
| bus rate | 99.99 MT/s (0.1 GT/s, 99,990 kT/s) + |
| bus speed | 99.99 MHz (0.1 GHz, 99,990 kHz) + |
| bus type | FSB + |
| clock multiplier | 4 + |
| core count | 1 + |
| core family | 5 + |
| core model | 13 + |
| core stepping | 0 +, 1 +, 2 + and 3 + |
| core voltage | 2 V (20 dV, 200 cV, 2,000 mV) + |
| core voltage tolerance | 0.1 V + |
| cpuid | 5D0 + |
| designer | AMD + |
| family | K6-III+ + |
| first announced | September 25, 2000 + |
| first launched | September 25, 2000 + |
| full page name | amd/k6-iii+/amd-k6-iiie+-400icr + |
| instance of | microprocessor + |
| io voltage | 3.368 V (33.675 dV, 336.75 cV, 3,367.5 mV) + |
| io voltage tolerance | 7% + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
| ldate | September 25, 2000 + |
| manufacturer | AMD + |
| market segment | Embedded + |
| max case temperature | 343.15 K (70 °C, 158 °F, 617.67 °R) + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max storage temperature | 423.15 K (150 °C, 302 °F, 761.67 °R) + |
| microarchitecture | K6-III + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min storage temperature | 208.15 K (-65 °C, -85 °F, 374.67 °R) + |
| model number | AMD-K6-IIIE+/400ICR + |
| name | AMD-K6-IIIE+/400ICR + |
| package | OBGA-349 + |
| part number | AMD-K6-IIIE+/400ICR + |
| platform | Super 7 + |
| process | 180 nm (0.18 μm, 1.8e-4 mm) + |
| series | K6-III+ Embedded + |
| smp max ways | 1 + |
| tdp | 9.5 W (9,500 mW, 0.0127 hp, 0.0095 kW) + |
| technology | CMOS + |
| thread count | 1 + |
| transistor count | 21,400,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |