Semiconductor & Computer Engineering
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Difference between revisions of "amd/am486/am486dx4-100sv8b"
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{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1 cache=8 | + | |l1 cache=8 KiB |
| − | |l1 break=1x8 | + | |l1 break=1x8 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
|l1 extra=(unified, write-back policy) | |l1 extra=(unified, write-back policy) | ||
Revision as of 21:49, 20 September 2016
Template:mpu Am486DX4-100SV8B was an Enhanced Am486 microprocessor introduced by AMD in 1996. This processor had a clock multiplier of 3 having a frequency of 100 MHz with a bus frequency of 33 MHz. This "Enhanced" Am486 includes some other features such as SMM, stop-clock control, and write-back cache. AMD later introduced the Am486DX4-100SV16B which was identical but had its L1$ doubled to 16 KB.
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-back policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- Stop-clock control
- System Management Mode (SMM)
Packaging
| Part | Package |
|---|---|
| A80486DX4-100SV8B | CPGA-168 |
| S80486DX4-100SV8B | SQFP-208 |
Documents
Gallery
See also
Facts about "Am486DX4-100SV8B - AMD"
| has feature | System Management Mode + |
| l1$ description | 4-way set associative + |
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |