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Difference between revisions of "intel/xeon e7/e7-4820"
< intel‎ | xeon e7

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|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 extra=(per core)
 
|l2 extra=(per core)
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|l3 cache=18 MB
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|l3 cache=18 MiB
−
|l3 break=
 
 
|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
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|l3 extra=
 
 
}}
 
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Revision as of 01:07, 19 September 2016

Template:mpu Xeon E7-4820 is a 64-bit octa-core x86 data center microprocessor that supports up to 4 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2 GHz with turob frequency of 2.266 GHz for 2 active cores. This chip has a TDP of 105 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.

Cache

Main article: Westmere § Cache
Cache Info [Edit Values]
L1I$ 256 KB
"KB" is not declared as a valid unit of measurement for this property.
 		8x32 KB 4-way set associative (per core)
L1D$ 256 KB
"KB" is not declared as a valid unit of measurement for this property.
 		8x32 KB 8-way set associative (per core)
L2$ 2 MB
"MB" is not declared as a valid unit of measurement for this property.
 		8x256 KB 8-way set associative (per core)
L3$ 18 MiB
18,432 KiB
18,874,368 B
0.0176 GiB
16-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3-800, DDR3-978, DDR3-1066
Controllers 1
Channels 4
ECC Support Yes
Max memory 2048 GB

Features

Template:mpu features

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Facts about "Xeon E7-4820 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description4-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ description16-way set associative +
l3$ size18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +