Difference between revisions of "intel/core i3/i3-6100h"

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Revision as of 00:51, 19 September 2016

Template:mpu Core i3-6100H is a 64-bit dual-core low-end mobile performance microprocessor introduced by Intel late 2015. This processor, which is based on the Skylake microarchitecture and manufactured in 14 nm process, has a base frequency of 2.7 GHz with a TDP of 35 W. This processor incorporates the HD Graphics 530 GPU clocked at 350 MHz with a max frequency of 900 MHz.

1 Cache
2 Graphics
3 Memory controller
4 Expansions
5 Features

Cache

Main article: Skylake § Cache

Cache Info [Edit Values]
L1I$	64 KB "KB" is not declared as a valid unit of measurement for this property.	2x32 KB 8-way set associative (per core, write-back)
L1D$	64 KB "KB" is not declared as a valid unit of measurement for this property.	2x32 KB 8-way set associative (per core, write-back)
L2$	512 KB "KB" is not declared as a valid unit of measurement for this property.	2x256 KB 4-way set associative (per core, write-back)
L3$	3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB	shared

Graphics

Integrated Graphic Information
GPU	Intel HD Graphics 530
Device ID	0x191B
Displays	3
Frequency	350 MHz 0.35 GHz 350,000 KHz
Max frequency	900 MHz 0.9 GHz 900,000 KHz
Max memory	64 GB "GB" is not declared as a valid unit of measurement for this property.
Output	DisplayPort, Embedded DisplayPort, HDMI, DVI
DirectX	12
OpenGL	4.4
OpenCL	2.0
HDMI	1.4a
DP	1.2
eDP	1.3
Max HDMI Res	4096x2304 @24 Hz
Max DP Res	4096x2304 @60 Hz
Max eDP Res	4096x2304 @60 Hz
	Intel Quick Sync Video
	Intel InTru 3D
	Intel Insider
	Intel WiDi (Wireless Display)
	Intel Clear Video

Memory controller

Integrated Memory Controller
Type	DDR3L-1600, LPDDR3-1866, DDR4-2133
Controllers	1
Channels	2
ECC Support	No
Max bandwidth	34.1 GB/s
Max memory	64 GB

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i3/i3-6100h&oldid=25064"

Facts about "Core i3-6100H - Intel"

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Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Core i3-6100H - Intel#package + and Core i3-6100H - Intel#io +
base frequency	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
clock multiplier	27 +
core count	2 +
core family	6 +
core model	94 +
core name	Skylake H +
core stepping	R0 +
core voltage (max)	1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)	0.55 V (5.5 dV, 55 cV, 550 mV) +
designer	Intel +
device id	0x191B +
die area	98.57 mm² (0.153 in², 0.986 cm², 98,570,000 µm²) +
die length	10.3 mm (1.03 cm, 0.406 in, 10,300 µm) +
die width	9.57 mm (0.957 cm, 0.377 in, 9,570 µm) +
family	Core i3 +
first announced	September 1, 2015 +
first launched	September 27, 2015 +
full page name	intel/core i3/i3-6100h +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	false +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, OS Guard +, Hyper-Threading Technology +, Secure Key Technology +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology +, Identity Protection Technology +, Extended Page Tables +, Memory Protection Extensions + and Software Guard Extensions +
has intel enhanced speedstep technology	true +
has intel flex memory access support	true +
has intel identity protection technology support	true +
has intel my wifi technology support	true +
has intel secure key technology	true +
has intel smart response technology support	true +
has intel supervisor mode execution protection	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	HD Graphics 530 +
integrated gpu base frequency	350 MHz (0.35 GHz, 350,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	24 +
integrated gpu max frequency	900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) +
isa	x86-64 +
isa family	x86 +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	4-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size	3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
last order	April 19, 2019 +
last shipment	October 18, 2019 +
ldate	September 27, 2015 +
main image	+
manufacturer	Intel +
market segment	Mobile +
max cpu count	1 +
max junction temperature	373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels	2 +
max operating temperature	100 °C +
max pcie lanes	16 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Skylake +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min operating temperature	0 °C +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	i3-6100H +
name	Core i3-6100H +
package	FCBGA-1440 +
part number	CL8066202194634 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 225.00 (€ 202.50, £ 182.25, ¥ 23,249.25) +
s-spec	SR2FR +
series	i3-6000 +
smp max ways	1 +
supported memory type	LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 +
tdp	35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technology	CMOS +
thread count	4 +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +
x86/has software guard extensions	true +

@@ Line 77: / Line 77: @@
 |l2 desc=4-way set associative
 |l2 extra=(per core, write-back)
-|l3 cache=3 MB
+|l3 cache=3 MiB
 |l3 desc=shared
 }}

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