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Difference between revisions of "pezy/pezy-scx/pezy-scnp"
< pezy‎ | pezy-scx

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'''PEZY-SCnp''' (SC - Super Computer; np - New Package) is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. PEZY-SC was As with the PEZ-SC, the SCnp is also manufactured on TSMC's 28HPC+ ([[28 nm process]]).
 
'''PEZY-SCnp''' (SC - Super Computer; np - New Package) is a revised version of the {{pezy|PEZY-SC}} model by [[PEZY]] introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. PEZY-SC was As with the PEZ-SC, the SCnp is also manufactured on TSMC's 28HPC+ ([[28 nm process]]).
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== Architecture ==
 +
{{main|pezy/pezy-sc|l1=PEZY-SC}}
 +
The PEZY-SCnp's architecture is identical to the {{pezy|PEZY-SC}}.
 +
 +
== Cache ==
 +
PEZY-SC's cache is separate from the {{armh|ARM926}}'s cache which has an L1$ of 32KB (2x) and 64KB L2$ (shared).
 +
{{cache info
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|l1i cache=2 MB
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|l1i break=1024x2 KB
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|l1i desc=
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|l1i extra=(per processor element)
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|l1d cache=1 MB
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|l1d break=512x2 KB
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|l1d desc=
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|l1d extra=(per 2 processor elements)
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|l2 cache=4 MB
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|l2 break=4x2 MB
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|l2 desc=
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|l2 extra=(per city)
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|l3 cache=8 MB
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|l3 break=4x2 MB
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|l3 desc=
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|l3 extra=(per prefecture)
 +
}}
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== Memory controller ==
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{{integrated memory controller
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| type              = DDR4-1866
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| controllers        = 1
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| channels          = 8
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| ecc support        = <!-- ?? -->
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| bandwidth schan    = 14,933 MB/s
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| bandwidth dchan    = 29,866 MB/s
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| bandwidth qchan    = 59,732 MB/s
 +
| bandwidth ochan    = 119,464 MB/s
 +
| max memory        =
 +
}}
 +
 +
== Expansions ==
 +
{{mpu expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 8
 +
| pcie config        =
 +
| pcie config 1      =
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| pcie config 2      =
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| usb revision      =
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| usb revision 2    =
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| usb ports          =
 +
| sata revision      =
 +
| sata ports        =
 +
| integrated lan    =
 +
| uart              = Yes
 +
| gp io              = Yes
 +
}}

Revision as of 19:17, 6 September 2016

Template:mpu PEZY-SCnp (SC - Super Computer; np - New Package) is a revised version of the PEZY-SC model by PEZY introduced in may of 2016. The new model uses a slightly larger package, lower core voltage, slightly higher core frequency, and thus higher performance. The PEZY-SCnp is said to deliver 1.57 TFLOPS (double-precision). PEZY also upgraded the connections from PCIe Gen2 to Gen3. PEZY-SC was As with the PEZ-SC, the SCnp is also manufactured on TSMC's 28HPC+ (28 nm process).

Architecture

Main article: PEZY-SC

The PEZY-SCnp's architecture is identical to the PEZY-SC.

Cache

PEZY-SC's cache is separate from the ARM926's cache which has an L1$ of 32KB (2x) and 64KB L2$ (shared).

Cache Info [Edit Values]
L1I$ 2 MB
"MB" is not declared as a valid unit of measurement for this property.
 		1024x2 KB (per processor element)
L1D$ 1 MB
"MB" is not declared as a valid unit of measurement for this property.
 		512x2 KB (per 2 processor elements)
L2$ 4 MB
"MB" is not declared as a valid unit of measurement for this property.
 		4x2 MB (per city)
L3$ 8 MB
"MB" is not declared as a valid unit of measurement for this property.
 		4x2 MB (per prefecture)

Memory controller

Integrated Memory Controller
Type DDR4-1866
Controllers 1
Channels 8
Bandwidth (single) 14,933 MB/s
Bandwidth (dual) 29,866 MB/s
Bandwidth (quad) 59,732 MB/s
Bandwidth (octa) 119,464 MB/s

Expansions

Template:mpu expansions

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