Difference between revisions of "intel/core m/m5-6y54"

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Revision as of 22:04, 3 September 2016

Template:mpu The Core M5-6Y54 is an ultra-low power dual-core 64-bit x86 microprocessor introduced by Intel in late 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.7 GHz. This chip, which is manufactured in 14 nm process based on the Skylake microarchitecture and incorporates Intel's HD Graphics 515 Gen9 GPU clocked at 300 MHz with turbo frequency of 900 MHz.

1 Cache
2 Graphics
3 Memory controller
4 Expansions
5 Features
6 Drivers

Cache

Main article: Skylake § Cache

Cache Info [Edit Values]
L1I$	64 KB "KB" is not declared as a valid unit of measurement for this property.	2x32 KB 8-way set associative (per core)
L1D$	64 KB "KB" is not declared as a valid unit of measurement for this property.	2x32 KB 8-way set associative (per core)
L2$	512 KB "KB" is not declared as a valid unit of measurement for this property.	2x256 KB 4-way set associative (per core)
L3$	4 MB "MB" is not declared as a valid unit of measurement for this property.	2x2 MB (shared LLC)

Graphics

Integrated Graphic Information
GPU	Intel HD Graphics 515
Device ID	0x191E
Execution Units	24
Displays	3
Frequency	300 MHz 0.3 GHz 300,000 KHz
Max frequency	900 MHz 0.9 GHz 900,000 KHz
Max memory	16 GB "GB" is not declared as a valid unit of measurement for this property.
Output	DisplayPort, Embedded DisplayPort, HDMI, DVI
DirectX	12
OpenGL	4.4
OpenCL	2.0
HDMI	1.4a
DP	1.2
eDP	1.3
Max HDMI Res	4096x2160 @24 Hz
Max DP Res	3840x2160 @60 Hz, 2880x1800 @60 Hz
Max eDP Res	3840x2160 @60 Hz, 2880x1800 @60 Hz
	Intel Quick Sync Video
	Intel InTru 3D
	Intel Insider
	Intel WiDi (Wireless Display)
	Intel Flexible Display Interface (FDI)
	Intel Clear Video

Memory controller

Integrated Memory Controller
Type	LPDDR3-1866, LPDDR3-1600
Controllers	1
Channels	2
ECC Support	No
Max bandwidth	29.8 GB/s
Max memory	16 GB

Expansions

Template:mpu expansions

Features

Template:mpu features

Drivers

Drivers

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_m/m5-6y54&oldid=23941"

Facts about "Core m5-6Y54 - Intel"

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Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Core m5-6Y54 - Intel#io +
base frequency	1,100 MHz (1.1 GHz, 1,100,000 kHz) +
bus type	DMI 3.0 +
clock multiplier	11 +
core count	2 +
core family	6 +
core model	78 +
core name	Skylake Y +
core stepping	D1 +
designer	Intel +
device id	0x191E +
die area	98.57 mm² (0.153 in², 0.986 cm², 98,570,000 µm²) +
die count	2 +
die length	10.3 mm (1.03 cm, 0.406 in, 10,300 µm) +
die width	9.57 mm (0.957 cm, 0.377 in, 9,570 µm) +
drivers url	https://downloadcenter.intel.com/product/94026 +
family	Core m5 +
first announced	September 1, 2015 +
first launched	September 27, 2015 +
full page name	intel/core m/m5-6y54 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	false +
has extended page tables support	true +
has feature	Hyper-Threading Technology +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Secure Key Technology +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Turbo Boost Technology 2.0 +, OS Guard +, Extended Page Tables +, Memory Protection Extensions + and Software Guard Extensions +
has intel enhanced speedstep technology	true +
has intel flex memory access support	true +
has intel my wifi technology support	true +
has intel secure key technology	true +
has intel smart response technology support	true +
has intel supervisor mode execution protection	true +
has intel turbo boost technology 2 0	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	HD Graphics 515 +
integrated gpu base frequency	300 MHz (0.3 GHz, 300,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	24 +
integrated gpu max frequency	900 MHz (0.9 GHz, 900,000 KHz) +
integrated gpu max memory	16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	4-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate	September 27, 2015 +
main image	+
manufacturer	Intel +
market segment	Mobile +
max cpu count	1 +
max junction temperature	373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory	16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth	27.81 GiB/s (28,477.44 MiB/s, 29.861 GB/s, 29,860.76 MB/s, 0.0272 TiB/s, 0.0299 TB/s) +
max memory channels	2 +
max pcie lanes	10 +
microarchitecture	Skylake +
min junction temperature	278.15 K (5 °C, 41 °F, 500.67 °R) +
model number	m5-6Y54 +
name	Core m5-6Y54 +
package	FCBGA-1515 +
part number	HE8066201930524 +
platform	Skylake +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 281.00 (€ 252.90, £ 227.61, ¥ 29,035.73) +
s-spec	SR2EM +
sdp	3 W (3,000 mW, 0.00402 hp, 0.003 kW) +
series	m-6Y +
smp max ways	1 +
supported memory type	LPDDR3-1866 + and DDR3L-1600 +
tdp	4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) +
tdp down	3.5 W (3,500 mW, 0.00469 hp, 0.0035 kW) +
tdp down frequency	600 MHz (0.6 GHz, 600,000 kHz) +
tdp up	7 W (7,000 mW, 0.00939 hp, 0.007 kW) +
tdp up frequency	1,500 MHz (1.5 GHz, 1,500,000 kHz) +
technology	CMOS +
thread count	4 +
transistor count	1,750,000,000 +
turbo frequency (1 core)	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (2 cores)	2,400 MHz (2.4 GHz, 2,400,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +
x86/has software guard extensions	true +

@@ Line 82: / Line 82: @@
 |l1d desc=8-way set associative
 |l1d extra=(per core)
-|l2 cache=512 MB
+|l2 cache=512 KB
 |l2 break=2x256 KB
 |l2 desc=4-way set associative

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