Semiconductor & Computer Engineering
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Difference between revisions of "Template:microarchitecture"
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{{#if:{{{OoOE|}}}|{{!}} '''OoOE''' {{!}}{{!}} {{{OoOE}}}|}} | {{#if:{{{OoOE|}}}|{{!}} '''OoOE''' {{!}}{{!}} {{{OoOE}}}|}} | ||
{{#if:{{{speculative|}}}|{{!-}}|<div></div>}} | {{#if:{{{speculative|}}}|{{!-}}|<div></div>}} | ||
| − | {{#if:{{{speculative|}}}|{{!}} '''Speculative | + | {{#if:{{{speculative|}}}|{{!}} '''Speculative Ex''' {{!}}{{!}} {{{speculative}}}|}} |
{{#if:{{{renaming|}}}|{{!-}}|<div></div>}} | {{#if:{{{renaming|}}}|{{!-}}|<div></div>}} | ||
| − | {{#if:{{{renaming|}}}|{{!}} ''' | + | {{#if:{{{renaming|}}}|{{!}} '''Reg Renaming''' {{!}}{{!}} {{{renaming}}}|}} |
{{#if:{{{stages|}}}|{{!-}}|<div></div>}} | {{#if:{{{stages|}}}|{{!-}}|<div></div>}} | ||
{{#if:{{{stages|}}}|{{!}} '''Stages''' {{!}}{{!}} [[pipeline stages::{{{stages}}}]]{{#if:{{{stages max|}}}|–[[pipeline stages::{{{stages max}}}]]}}|}} | {{#if:{{{stages|}}}|{{!}} '''Stages''' {{!}}{{!}} [[pipeline stages::{{{stages}}}]]{{#if:{{{stages max|}}}|–[[pipeline stages::{{{stages max}}}]]}}|}} | ||
Revision as of 10:53, 18 July 2016
Code
{{microarchitecture
| atype = "CPU" or "GPU" (meta-related)
| name =
| designer =
| manufacturer =
| introduction =
| phase-out =
| process =
| cores =
| cores 2 =
| cores N =
| type = <!-- e.g. "Superscalar" -->
| type 2 =
| type N =
| oooe = <!-- Yes or No only -->
| speculative = <!-- Yes or No only -->
| renaming = <!-- Yes or No only -->
| stages = <!-- ONLY IF FIXED SIZE, otherwise use below for range -->
| stages min =
| stages max =
| decode = 2-way
| isa =
| isa 2 =
| isa N =
| feature =
| extension =
| extension 2 =
| extension N =
| l1i =
| l1i per =
| l1i desc =
| l1d =
| l1d per =
| l1d desc =
| l2 =
| l2 per =
| l2 desc =
| l3 =
| l3 per =
| l3 desc =
| core name =
| core name 2 =
| core name N =
| predecessor =
| predecessor link =
| successor =
| successor link =
| successor 2 =
| successor 2 link =
| successor N =
| successor N link =
}}