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Difference between revisions of "Talk:intel/microarchitectures/broadwell (client)"
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(→‎dubious intel statement on scheduler size: new section)
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According to the Intel presentation slides, they have "Larger out-of-order scheduler" but what's not clear is what they meant by that. The ROB seems to remain at 192 entries. Scheduler is still at 60 entries. Or am I missing something? --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 16:20, 14 April 2016 (EDT)
 
According to the Intel presentation slides, they have "Larger out-of-order scheduler" but what's not clear is what they meant by that. The ROB seems to remain at 192 entries. Scheduler is still at 60 entries. Or am I missing something? --[[User:At32Hz|At32Hz]] ([[User talk:At32Hz|talk]]) 16:20, 14 April 2016 (EDT)
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It's increased to 64. I can't find the original Intel source, but its reflected here:
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https://www.microway.com/knowledge-center-articles/detailed-specifications-of-the-intel-xeon-e5-2600v4-broadwell-ep-processors/
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Also the instruction queue is increased from 2x20 to 2x25, but [citation needed] I guess, can't find it anymore :)

Revision as of 15:53, 17 July 2016

This is the discussion page for the intel/microarchitectures/broadwell (client) page.

dubious intel statement on scheduler size

According to the Intel presentation slides, they have "Larger out-of-order scheduler" but what's not clear is what they meant by that. The ROB seems to remain at 192 entries. Scheduler is still at 60 entries. Or am I missing something? --At32Hz (talk) 16:20, 14 April 2016 (EDT)


It's increased to 64. I can't find the original Intel source, but its reflected here: https://www.microway.com/knowledge-center-articles/detailed-specifications-of-the-intel-xeon-e5-2600v4-broadwell-ep-processors/

Also the instruction queue is increased from 2x20 to 2x25, but [citation needed] I guess, can't find it anymore :)

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