Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intrinsity/fastmath/fastmath-lp"
| Line 120: | Line 120: | ||
* [[has feature::JTAG]] interface | * [[has feature::JTAG]] interface | ||
* 8-bit or 32-bit wide bus operates up to 66 MHz | * 8-bit or 32-bit wide bus operates up to 66 MHz | ||
| + | |||
| + | == Documents == | ||
| + | === Manuals === | ||
| + | * [[:File:FastMATH Product Brief.pdf|FastMATH Product Brief]] | ||
Revision as of 16:32, 3 July 2016
Template:mpu The FastMATH-LP was a microprocessor developed by Intrinsity operating at 1 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.
Contents
Cache
- Main article: FastMATH § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KB "KB" is not declared as a valid unit of measurement for this property. |
1x16 KB 256 blocks × 16 words/block |
| L1D$ | 16 KB "KB" is not declared as a valid unit of measurement for this property. |
1x16 KB 256 blocks × 16 words/block write-through or write-back mode |
| L2$ | 1 MB "MB" is not declared as a valid unit of measurement for this property. |
1x1 MB 4-way set associative (configurable as SRAM in 256 KB increments) |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR-400 |
| Controllers | 1 |
| Channels | 2 |
| Max memory | 1 GB |
Matrix and Vector Unit
- SIMD architecture
- Operates on 4x4 array of 32-bit elements
- Fixed-point matrix, vector, and scalar data types
Features
- JTAG interface
- 8-bit or 32-bit wide bus operates up to 66 MHz
Documents
Manuals
Facts about "FastMATH-LP - Intrinsity"
| has feature | JTAG + |
| l1d$ description | 256 blocks × 16 words/block + |
| l1i$ description | 256 blocks × 16 words/block + |
| l2$ description | 4-way set associative + |