From WikiChip
Difference between revisions of "intrinsity/fastmath/fastmath-lp"
< intrinsity‎ | fastmath

Line 75: Line 75:
 
}}
 
}}
 
The '''FastMATH-LP''' was a microprocessor developed by [[Intrinsity]] operating at 1 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.
 
The '''FastMATH-LP''' was a microprocessor developed by [[Intrinsity]] operating at 1 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.
 +
 +
== Cache ==
 +
{{main|intrinsity/microarchitectures/fastmath#Memory_Hierarchy|l1=FastMATH § Cache}}
 +
{{cache info
 +
|l1i cache=16 KB
 +
|l1i break=1x16 KB
 +
|l1i desc=256 blocks × 16 words/block
 +
|l1i extra=
 +
|l1d cache=16 KB
 +
|l1d break=1x16 KB
 +
|l1d desc=256 blocks × 16 words/block
 +
|l1d extra=write-through or write-back mode
 +
|l2 cache=1 MB
 +
|l2 break=1x1 MB
 +
|l2 desc=4-way set associative
 +
|l2 extra=(configurable as SRAM in 256 KB increments)
 +
|l3 cache=
 +
|l3 break=
 +
|l3 desc=
 +
|l3 extra=
 +
}}
 +
 +
== Graphics ==
 +
This SoC has no integrated graphics processing unit.
 +
 +
== Memory controller ==
 +
{{integrated memory controller
 +
| type              = DDR-400
 +
| controllers        = 1
 +
| channels          = 2
 +
| ecc support        =
 +
| max bandwidth      =
 +
| bandwidth schan    =
 +
| bandwidth dchan    =
 +
| max memory        = 1 GB
 +
}}
 +
 +
== Matrix and Vector Unit ==
 +
* SIMD architecture
 +
* Operates on 4x4 array of {{arch|32}} elements
 +
* Fixed-point matrix, vector, and scalar data types
 +
 +
== Features ==
 +
* [[has feature::JTAG]] interface
 +
* 8-bit or 32-bit wide bus operates up to 66 MHz

Revision as of 16:14, 3 July 2016

Template:mpu The FastMATH-LP was a microprocessor developed by Intrinsity operating at 1 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.

Cache

Main article: FastMATH § Cache
Cache Info [Edit Values]
L1I$ 16 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x16 KB 256 blocks × 16 words/block
L1D$ 16 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x16 KB 256 blocks × 16 words/block write-through or write-back mode
L2$ 1 MB
"MB" is not declared as a valid unit of measurement for this property.
 		1x1 MB 4-way set associative (configurable as SRAM in 256 KB increments)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR-400
Controllers 1
Channels 2
Max memory 1 GB

Matrix and Vector Unit

  • SIMD architecture
  • Operates on 4x4 array of 32-bit elements
  • Fixed-point matrix, vector, and scalar data types

Features

  • JTAG interface
  • 8-bit or 32-bit wide bus operates up to 66 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intrinsity/fastmath/fastmath-lp&oldid=22672"
Facts about "FastMATH-LP - Intrinsity"
RDF feed
has featureJTAG +
l1d$ description256 blocks × 16 words/block +
l1i$ description256 blocks × 16 words/block +
l2$ description4-way set associative +