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Difference between revisions of "intrinsity/fastmath/fastmath-2"
< intrinsity‎ | fastmath

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The '''FastMATH 2 GHz''' was the flagship microprocessor developed by [[Intrinsity]] operating at 2 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.
 
The '''FastMATH 2 GHz''' was the flagship microprocessor developed by [[Intrinsity]] operating at 2 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit.
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== Cache ==
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{{main|intrinsity/microarchitectures/fastmath#Memory_Hierarchy|l1=FastMATH § Cache}}
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{{cache info
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|l1i cache=16 KB
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|l1i break=1x16 KB
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|l1i desc=256 blocks × 16 words/block
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|l1i extra=
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|l1d cache=16 KB
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|l1d break=1x16 KB
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|l1d desc=256 blocks × 16 words/block
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|l1d extra=write-through or write-back mode
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|l2 cache=1 MB
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|l2 break=1x1 MB
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|l2 desc=4-way set associative
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|l2 extra=(configurable as SRAM in 256 KB increments)
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|l3 cache=
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|l3 break=
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|l3 desc=
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|l3 extra=
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}}
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== Graphics ==
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This SoC has no integrated graphics processing unit.
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== Memory controller ==
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{{integrated memory controller
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| type              = DDR-400
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| controllers        = 1
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| channels          = 2
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| ecc support        =
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| max bandwidth      =
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| bandwidth schan    =
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| bandwidth dchan    =
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| max memory        = 1 GB
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}}
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== Matrix and Vector Unit ==
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* SIMD architecture
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* Operates on 4x4 array of {{arch|32}} elements
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* Fixed-point matrix, vector, and scalar data types
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== Features ==
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* [[has feature::JTAG]] interface
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* 8-bit or 32-bit wide bus operates up to 66 MHz

Revision as of 17:14, 3 July 2016

Template:mpu The FastMATH 2 GHz was the flagship microprocessor developed by Intrinsity operating at 2 GHz. The processor incorporates a high-performance MIPS CPU along with a powerful matrix and vector math unit.

Cache

Main article: FastMATH § Cache
Cache Info [Edit Values]
L1I$ 16 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x16 KB 256 blocks × 16 words/block
L1D$ 16 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x16 KB 256 blocks × 16 words/block write-through or write-back mode
L2$ 1 MB
"MB" is not declared as a valid unit of measurement for this property.
 		1x1 MB 4-way set associative (configurable as SRAM in 256 KB increments)

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR-400
Controllers 1
Channels 2
Max memory 1 GB

Matrix and Vector Unit

  • SIMD architecture
  • Operates on 4x4 array of 32-bit elements
  • Fixed-point matrix, vector, and scalar data types

Features

  • JTAG interface
  • 8-bit or 32-bit wide bus operates up to 66 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intrinsity/fastmath/fastmath-2&oldid=22670"
Facts about "FastMATH 2 GHz - Intrinsity"
RDF feed
base frequency2,000 MHz (2 GHz, 2,000,000 kHz) +
bus rate4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus speed500 MHz (0.5 GHz, 500,000 kHz) +
bus typeRapidIO +
core count1 +
core voltage1 V (10 dV, 100 cV, 1,000 mV) +
designerIntrinsity +
familyFastMATH +
first announced2001 +
first launched2002 +
full page nameintrinsity/fastmath/fastmath-2 +
has featureJTAG +
instance ofmicroprocessor +
l1d$ description256 blocks × 16 words/block +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description256 blocks × 16 words/block +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate2002 +
manufacturerTSMC +
market segmentEmbedded +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
microarchitectureFashMATH +
model numberFastMATH-2 +
nameFastMATH 2 GHz +
power dissipation15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
technologyDynamic CMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +