From WikiChip
Difference between revisions of "ambric/am2000/am2035"
Line 40: | Line 40: | ||
| thread count = | | thread count = | ||
| max cpus = | | max cpus = | ||
− | | max memory = | + | | max memory = 4 GB |
| electrical = | | electrical = | ||
Line 98: | Line 98: | ||
| bandwidth schan = | | bandwidth schan = | ||
| bandwidth dchan = | | bandwidth dchan = | ||
− | | max memory = | + | | max memory = 4 GB |
}} | }} | ||
Revision as of 17:05, 24 June 2016
Template:mpu Am2035 was an MPPA introduced in late 2006 by Ambric. This model was made of 35 Brics arranged as a grid, making up a total of 280 32-bit RICS-like cores operating asynchronously at 1-333 MHz.
Architecture
- Main article: Am2000 § Architecture
The Am2035 is made of 35 homogeneous 'Brics' laid out in a grid to form 280 cores and 280 RAM units.
General layout:
- 35x Brics
Cache
The Am2035 contains 35 Brics, each with its own RAM Unit (RU) of 13 kB of SRAM for a total of 455 kB of SRAM.
Memory controller
Integrated Memory Controller | |
Type | DDR2-400 |
Controllers | 2 |
Channels | 1 |
Max memory | 4 GB |
Expansions
- PCIe
- JTAG
- GPIO @ 100 MHz
- serial flash