Semiconductor & Computer Engineering
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Difference between revisions of "ambric/am2000/am2045"
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| frequency = 333 MHz | | frequency = 333 MHz | ||
| bus type = | | bus type = | ||
| − | | bus speed = | + | | bus speed = 100 MHz |
| bus rate = | | bus rate = | ||
| − | | clock multiplier = | + | | clock multiplier = 3.3 |
| microarch = Ambric | | microarch = Ambric | ||
| Line 73: | Line 73: | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
}} | }} | ||
| + | '''Am2045''' (later renamed '''Am2045A''') was [[Ambric]]'s original flagship [[MPPA]] introduced in late 2006. This model was made of {{ambric|am2000#Architecture|45 Brics}} arranged as a grid of 5x9, making up a total of 360 {{arch|32}} [[RICS]]-like cores operating asynchronously at 1-333 MHz. | ||
| + | |||
| + | == Architecture == | ||
| + | {{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}} | ||
| + | The Am2045 is made of 45 homogeneous 'Brics' laid out in a 5 by 9 grid to form 360 cores and 360 RAM units. | ||
| + | |||
| + | General layout: | ||
| + | * 45x Brics | ||
| + | ** 2x Computer Unit (CU) | ||
| + | *** 2x SRD {{arch|32}} CPU | ||
| + | *** 2x RD {{arch|32}} CPU | ||
| + | ** 2x [[RAM]] Unit (RU) | ||
| + | *** 4x 2 KB [[SRAM]] bank | ||
| + | |||
| + | == Cache == | ||
| + | The Am2045 contains 45 Brics, each with its own [[RAM]] Unit (RU) of 13 kB of SRAM for a total of 585 kB of SRAM. | ||
| + | |||
| + | == Memory controller == | ||
| + | {{integrated memory controller | ||
| + | | type = DDR2-400 | ||
| + | | controllers = 2 | ||
| + | | channels = 1 | ||
| + | | ecc support = | ||
| + | | max bandwidth = | ||
| + | | bandwidth schan = | ||
| + | | bandwidth dchan = | ||
| + | | max memory = | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | * [[has feature::PCIe]] | ||
| + | * [[has feature::JTAG]] | ||
| + | * 128x [[has feature::GPIO]] @ 100 MHz | ||
| + | * [[has feature::serial flash]] | ||
Revision as of 15:47, 24 June 2016
Template:mpu Am2045 (later renamed Am2045A) was Ambric's original flagship MPPA introduced in late 2006. This model was made of 45 Brics arranged as a grid of 5x9, making up a total of 360 32-bit RICS-like cores operating asynchronously at 1-333 MHz.
Architecture
- Main article: Am2000 § Architecture
The Am2045 is made of 45 homogeneous 'Brics' laid out in a 5 by 9 grid to form 360 cores and 360 RAM units.
General layout:
- 45x Brics
Cache
The Am2045 contains 45 Brics, each with its own RAM Unit (RU) of 13 kB of SRAM for a total of 585 kB of SRAM.
Memory controller
| Integrated Memory Controller | |
| Type | DDR2-400 |
| Controllers | 2 |
| Channels | 1 |
Expansions
- PCIe
- JTAG
- 128x GPIO @ 100 MHz
- serial flash