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Difference between revisions of "ambric/am2000/am2045"
< ambric‎ | am2000

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| frequency          = 333 MHz
 
| frequency          = 333 MHz
 
| bus type            =  
 
| bus type            =  
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| bus speed          =  
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| bus speed          = 100 MHz
 
| bus rate            =  
 
| bus rate            =  
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| clock multiplier    =  
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| clock multiplier    = 3.3
  
 
| microarch          = Ambric  
 
| microarch          = Ambric  
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| socket 0 type      = BGA
 
| socket 0 type      = BGA
 
}}
 
}}
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'''Am2045''' (later renamed '''Am2045A''') was [[Ambric]]'s original flagship [[MPPA]] introduced in late 2006. This model was made of {{ambric|am2000#Architecture|45 Brics}} arranged as a grid of 5x9, making up a total of 360 {{arch|32}} [[RICS]]-like cores operating asynchronously at 1-333 MHz.
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== Architecture ==
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{{main|ambric/am2000#Architecture|l1=Am2000 § Architecture}}
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The Am2045 is made of 45 homogeneous 'Brics' laid out in a 5 by 9 grid to form 360 cores and 360 RAM units.
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General layout:
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* 45x Brics
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** 2x Computer Unit (CU)
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*** 2x SRD {{arch|32}} CPU
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*** 2x RD {{arch|32}} CPU
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** 2x [[RAM]] Unit (RU)
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*** 4x 2 KB [[SRAM]] bank
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== Cache ==
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The Am2045 contains 45 Brics, each with its own [[RAM]] Unit (RU) of 13 kB of SRAM for a total of 585 kB of SRAM.
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== Memory controller ==
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{{integrated memory controller
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| type              = DDR2-400
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| controllers        = 2
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| channels          = 1
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| ecc support        =
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| max bandwidth      =
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| bandwidth schan    =
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| bandwidth dchan    =
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| max memory        =
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}}
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== Expansions ==
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* [[has feature::PCIe]]
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* [[has feature::JTAG]]
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* 128x [[has feature::GPIO]] @ 100 MHz
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* [[has feature::serial flash]]

Revision as of 16:47, 24 June 2016

Template:mpu Am2045 (later renamed Am2045A) was Ambric's original flagship MPPA introduced in late 2006. This model was made of 45 Brics arranged as a grid of 5x9, making up a total of 360 32-bit RICS-like cores operating asynchronously at 1-333 MHz.

Architecture

Main article: Am2000 § Architecture

The Am2045 is made of 45 homogeneous 'Brics' laid out in a 5 by 9 grid to form 360 cores and 360 RAM units.

General layout:

  • 45x Brics

Cache

The Am2045 contains 45 Brics, each with its own RAM Unit (RU) of 13 kB of SRAM for a total of 585 kB of SRAM.

Memory controller

Integrated Memory Controller
Type DDR2-400
Controllers 2
Channels 1

Expansions

  • PCIe
  • JTAG
  • 128x GPIO @ 100 MHz
  • serial flash
Retrieved from "https://en.wikichip.org/w/index.php?title=ambric/am2000/am2045&oldid=22343"
Facts about "Am2045 - Ambric"
RDF feed
base frequency333 MHz (0.333 GHz, 333,000 kHz) +
bus speed100 MHz (0.1 GHz, 100,000 kHz) +
clock multiplier3.3 +
codenameKestrel +
core count344 +
designerAmbric +
familyAm2000 +
first announcedOctober 10, 2006 +
first launchedJanuary 2007 +
full page nameambric/am2000/am2045 +
has featurePCIe +, JTAG +, GPIO + and serial flash +
has locked clock multiplierfalse +
instance ofmicroprocessor +
last order2012 +
last shipment2012 +
ldateJanuary 2007 +
main imageFile:ambric 2045.gif +
main image captionAm2045 +
market segmentEmbedded +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
microarchitectureAmbric +
model numberAm2045 +
nameAm2045 +
part numberAm2045 + and Am2045A +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesGen 1 +
technologyCMOS +
transistor count117,000,000 +
word size32 bit (4 octets, 8 nibbles) +