Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "amd/am486/am486dx4-100sv8b"
| Line 115: | Line 115: | ||
* [[:File:AMD Enhanced Am486 (March, 1996).pdf|AMD Enhanced Am486 (March, 1996)]] | * [[:File:AMD Enhanced Am486 (March, 1996).pdf|AMD Enhanced Am486 (March, 1996)]] | ||
| + | == Gallery == | ||
| + | <gallery> | ||
| + | File:AMD Am486DX4 100MHz 2007 03 27.jpg | ||
| + | </gallery> | ||
== See also == | == See also == | ||
* {{amd|Am486|Am486 family}} | * {{amd|Am486|Am486 family}} | ||
Revision as of 03:11, 17 May 2016
Template:mpu Am486DX4-100SV8B was an Enhanced Am486 microprocessor introduced by AMD in 1996. This processor had a clock multiplier of 3 having a frequency of 100 MHz with a bus frequency of 33 MHz. This "Enhanced" Am486 includes some other features such as SMM, stop-clock control, and write-back cache. AMD later introduced the Am486DX4-100SV16B which was identical but had its L1$ doubled to 16 KB.
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-back policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- Stop-clock control
- System Management Mode (SMM)
Packaging
| Part | Package |
|---|---|
| A80486DX4-100SV8B | CPGA-168 |
| S80486DX4-100SV8B | SQFP-208 |
Documents
Gallery
See also
Facts about "Am486DX4-100SV8B - AMD"
| has feature | System Management Mode + |
| l1$ description | 4-way set associative + |