From WikiChip
Difference between revisions of "amd/am486/am486dx2-66nv8t"
Line 63: | Line 63: | ||
| packaging = Yes | | packaging = Yes | ||
− | | package | + | | package 0 = CPGA-168 |
− | | package type | + | | package 0 type = CPGA |
− | | package pitch | + | | package 0 pins = 168 |
− | | package | + | | package 0 pitch = 2.286 mm |
− | | socket | + | | package 0 width = 44.069 mm |
− | | socket 2 | + | | package 0 length = 44.069 mm |
− | | socket 3 | + | | package 0 height = 3.556 mm |
+ | | socket 0 = Socket 1 | ||
+ | | socket 0 type = | ||
+ | | socket 0 2 = Socket 2 | ||
+ | | socket 0 2 type = | ||
+ | | socket 0 3 = Socket 3 | ||
+ | | socket 0 3 type = | ||
}} | }} | ||
'''Am486DX2-66NV8T''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 2 having base frequency of 66 MHz with a bus frequency of 33 MHz. This model is is a modified version of {{\\|Am486DX2-66V8T}} (and earlier {{\\|Am486DX2-66}}) that no longer included Intel's ICE microcode. | '''Am486DX2-66NV8T''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 2 having base frequency of 66 MHz with a bus frequency of 33 MHz. This model is is a modified version of {{\\|Am486DX2-66V8T}} (and earlier {{\\|Am486DX2-66}}) that no longer included Intel's ICE microcode. |
Revision as of 22:37, 16 May 2016
Template:mpu Am486DX2-66NV8T was an 80486-compatible microprocessor introduced by AMD in 1995 following the conclusion of the legal battle with Intel. This processor had a clock multiplier of 2 having base frequency of 66 MHz with a bus frequency of 33 MHz. This model is is a modified version of Am486DX2-66V8T (and earlier Am486DX2-66) that no longer included Intel's ICE microcode.
Contents
Cache
- Main article: 80486 § Cache
Cache Info [Edit Values] | ||
L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.