From WikiChip
Difference between revisions of "intel/80486/486dx4-100"
< intel‎ | 80486

Line 31: Line 31:
 
| bus rate            = 33 MT/s
 
| bus rate            = 33 MT/s
 
| clock multiplier    = 3
 
| clock multiplier    = 3
| s-spec              =  
+
| s-spec              = SK050
 +
| s-spec 2            = SK051
 +
| s-spec 3            = SK096
 +
| s-spec 4            = SK851
 +
| s-spec 5            = SX877
 +
| s-spec 6            = SX900
 +
| s-spec 7            = SX908
 
| s-spec es          =  
 
| s-spec es          =  
| s-spec qs          =  
+
| s-spec qs          = Q0746
| cpuid              =  
+
| cpuid              = 480
 +
| cpuid              = 483
  
 
| microarch          = 80486
 
| microarch          = 80486
Line 53: Line 60:
  
 
| electrical          = Yes
 
| electrical          = Yes
| power              =  
+
| power              = 3.55 W
| v core              = 5 V
+
| v core              = 3.3 V
| v core tolerance    =  
+
| v core tolerance    = 0.3 V
| v core 2            = 3.3 V
 
| v core 2 tolerance  =
 
 
| temp max            = 85 °C
 
| temp max            = 85 °C
 
| temp min            = 0 °C
 
| temp min            = 0 °C

Revision as of 16:37, 11 May 2016

Template:mpu i486DX4-100 was a fourth-generation x86 microprocessor introduced by Intel in 1994. This chip, which is based on the 80486 microarchitecture, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 100 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM). The DX4 series had twice as much cache space as the older processors.

Cache

Main article: 80486 § Cache
Cache Info [Edit Values]
L1$ 16 KB
"KB" is not declared as a valid unit of measurement for this property.
1x16 KB 4-way set associative (unified, write-through policy)

Graphics

This chip had no integrated graphics processing unit.

Features

See also

Facts about "i486DX4-100 - Intel"
l1$ description4-way set associative +