From WikiChip
Difference between revisions of "intel/80486/486dx2-50"
< intel‎ | 80486

Line 28: Line 28:
 
| bus rate            = 25 MT/s
 
| bus rate            = 25 MT/s
 
| clock multiplier    = 2
 
| clock multiplier    = 2
| s-spec              =  
+
| s-spec              = SX845
 
| s-spec es          =  
 
| s-spec es          =  
| s-spec qs          =  
+
| s-spec qs          = Q0498
| cpuid              =  
+
| s-spec qs 2        = Q0576
 +
| cpuid              = 45B
  
 
| microarch          = 80486
 
| microarch          = 80486
Line 51: Line 52:
  
 
| electrical          = Yes
 
| electrical          = Yes
| power              =  
+
| power              = 3.08 W
 
| v core              = 5 V
 
| v core              = 5 V
| v core tolerance    =  
+
| v core tolerance    = 5%
 
| temp max            = 85 °C
 
| temp max            = 85 °C
 
| temp min            = 0 °C
 
| temp min            = 0 °C

Revision as of 15:27, 11 May 2016

Template:mpu i486DX2-50 was a fourth-generation x86 microprocessor introduced by Intel in 1992. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).

Cache

Main article: 80486 § Cache
Cache Info [Edit Values]
L1$ 8 KB
"KB" is not declared as a valid unit of measurement for this property.
1x8 KB 4-way set associative (unified, write-through policy )

Graphics

This chip had no integrated graphics processing unit.

Features

See also

Facts about "i486DX2-50 - Intel"
l1$ description4-way set associative +