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Difference between revisions of "intel/80486/486dx4-75"
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'''i486DX4-75''' was a fourth-generation [[x86]] [[microprocessor]] introduced by [[Intel]] in 1992. This chip, which is based on the {{intel|microarchitectures/80486|80486 microarchitecture}}, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 75 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). The DX4 series had twice as much cache space as the older processors.
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'''i486DX4-75''' was a fourth-generation [[x86]] [[microprocessor]] introduced by [[Intel]] in 1994. This chip, which is based on the {{intel|microarchitectures/80486|80486 microarchitecture}}, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 75 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). The DX4 series had twice as much cache space as the older processors.
  
 
== Cache ==
 
== Cache ==

Revision as of 14:11, 11 May 2016

Template:mpu i486DX4-75 was a fourth-generation x86 microprocessor introduced by Intel in 1994. This chip, which is based on the 80486 microarchitecture, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 75 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM). The DX4 series had twice as much cache space as the older processors.

Cache

Main article: 80486 § Cache
Cache Info [Edit Values]
L1$ 16 KB
"KB" is not declared as a valid unit of measurement for this property.
1x16 KB 4-way set associative (unified, write-through policy)

Graphics

This chip had no integrated graphics processing unit.

Features

See also

Facts about "i486DX4-75 - Intel"
l1$ description4-way set associative +