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Difference between revisions of "intel/80486/486dx4-100"
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| core stepping = | | core stepping = | ||
| process = 600 nm | | process = 600 nm | ||
| − | | transistors = | + | | transistors = 1,600,000 |
| technology = CMOS | | technology = CMOS | ||
| die size = | | die size = | ||
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| socket 4 = Socket 6 | | socket 4 = Socket 6 | ||
}} | }} | ||
| + | '''i486DX4-100''' was a fourth-generation [[x86]] [[microprocessor]] introduced by [[Intel]] in 1994. This chip, which is based on the {{intel|microarchitectures/80486|80486 microarchitecture}}, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 100 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). The DX4 series had twice as much cache space as the older processors. | ||
| + | |||
| + | == Cache == | ||
| + | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
| + | {{cache info | ||
| + | |l1 cache=16 KB | ||
| + | |l1 break=1x16 KB | ||
| + | |l1 desc=4-way set associative | ||
| + | |l1 extra=(unified, write-through policy) | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This chip had no integrated graphics processing unit. | ||
| + | |||
| + | == Features == | ||
| + | * {{intel|System Management Mode}} (SMM) | ||
| + | |||
| + | == See also == | ||
| + | * {{intel|80486|80486 family}} | ||
Revision as of 15:11, 11 May 2016
Template:mpu i486DX4-100 was a fourth-generation x86 microprocessor introduced by Intel in 1994. This chip, which is based on the 80486 microarchitecture, had a clock multiplier of x2, x2.5, and x3 with a max operating frequency of 100 MHz, three times the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM). The DX4 series had twice as much cache space as the older processors.
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 16 KB "KB" is not declared as a valid unit of measurement for this property. |
1x16 KB 4-way set associative (unified, write-through policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
See also
Facts about "i486DX4-100 - Intel"
| base frequency | 100 MHz (0.1 GHz, 100,000 kHz) + |
| bus rate | 33 MT/s (0.033 GT/s, 33,000 kT/s) + |
| bus speed | 33 MHz (0.033 GHz, 33,000 kHz) + |
| bus type | FSB + |
| clock multiplier | 3 + |
| core count | 1 + |
| core name | 486DX4 + |
| core voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
| core voltage tolerance | 0.3 V + |
| cpuid | 480 + and 483 + |
| designer | Intel + |
| family | 80486 + |
| first launched | March 7, 1994 + |
| full page name | intel/80486/486dx4-100 + |
| instance of | microprocessor + |
| l1$ description | 4-way set associative + |
| l1$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| ldate | March 7, 1994 + |
| main image |  + |
| main image caption | A80486DX4-100, S-Spec SX900 + |
| manufacturer | Intel + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max operating temperature | 85 °C + |
| microarchitecture | 80486 + |
| min operating temperature | 0 °C + |
| model number | i486DX4-100 + |
| name | Intel i486DX4-100 + |
| part number | A80486DX4-100 +, A80486DX4WB100 +, MA80486DX4-100 +, TQ80486DX4100 +, MQ80486DX4-100 +, MQ80486DX4100 +, FC80486DX4-100 + and FC80486DX4WB100 + |
| power dissipation | 3.55 W (3,550 mW, 0.00476 hp, 0.00355 kW) + |
| process | 600 nm (0.6 μm, 6.0e-4 mm) + |
| s-spec | SK050 +, SK051 +, SK096 +, SK851 +, SX877 +, SX900 +, SX908 +, SK053 +, SK063 +, SK099 +, SL2M9 +, SX876 + and SX906 + |
| series | 486DX4 + |
| smp max ways | 1 + |
| technology | CMOS + |
| transistor count | 1,600,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |
