Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/80486/486dx2-50"
| Line 69: | Line 69: | ||
| socket 3 = Socket 3 | | socket 3 = Socket 3 | ||
}} | }} | ||
| + | '''i486DX2-50''' was a fourth-generation [[x86]] [[microprocessor]] introduced by [[Intel]] in 1992. This chip, which is based on the {{intel|microarchitectures/80486|80486 microarchitecture}}, had a clock doubler operating at 50 MHz, twice the bus frequency. Like the original i486DX, this chip implemented the {{intel|80387}} [[FPU]] on-die and incorporated {{intel|System Management Mode}} (SMM). | ||
| + | |||
| + | == Cache == | ||
| + | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
| + | {{cache info | ||
| + | |l1 cache=8 KB | ||
| + | |l1 break=1x8 KB | ||
| + | |l1 desc=4-way set associative | ||
| + | |l1 extra=(unified, write-through policy ) | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This chip had no integrated graphics processing unit. | ||
| + | |||
| + | == Features == | ||
| + | * {{intel|System Management Mode}} (SMM) | ||
| + | |||
| + | == See also == | ||
| + | * {{intel|80486|80486 family}} | ||
Revision as of 14:05, 11 May 2016
Template:mpu i486DX2-50 was a fourth-generation x86 microprocessor introduced by Intel in 1992. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 50 MHz, twice the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).
Contents
Cache
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative (unified, write-through policy ) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)