Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon d/d-1518"
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| KR interface = No | | KR interface = No | ||
| KR4 Interface = No | | KR4 Interface = No | ||
| − | | KX | + | | KX interface = Yes |
| − | | KX4 | + | | KX4 interface = No |
| 10Base-T = No | | 10Base-T = No | ||
| 100Base-T = No | | 100Base-T = No | ||
Revision as of 14:56, 7 May 2016
Template:mpu The Xeon D-1518 is a 64-bit quad-core x86-64 microserver SoC that was introduced by Intel in March of 2015. The D-1518 operates at 2 GHz. This chip, which is based on the Broadwell microarchitecture and manufactured in 14 nm process, has a TDP of 35 W and can support up to 128 GB of RAM (DDR3L/DDR4).
Cache
- Main article: Broadwell's Cache
| Cache Info [Edit Values] | ||
| L1I$ | 128 KB "KB" is not declared as a valid unit of measurement for this property. |
4x32 KB 8-way set associative (per core) |
| L1D$ | 128 KB "KB" is not declared as a valid unit of measurement for this property. |
4x32 KB 8-way set associative (per core) |
| L2$ | 1 MB "MB" is not declared as a valid unit of measurement for this property. |
4x256 KB 8-way set associative (per core) |
| L3$ | 6 MB "MB" is not declared as a valid unit of measurement for this property. |
4x1.5 MB (per core) |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR3L-1333, DDR3L-1600, DDR4-1600, DDR4-1867, DDR4-2133 |
| Controllers | 1 |
| Channels | 2 |
| ECC Support | Yes |
| Max memory | 128 GB |
Expansions
Networking
| Networking | |
| SFI interface | Yes |
| KR interface | No |
| KX interface | Yes |
| KX4 interface | No |
| 10Base-T | No |
| 100Base-T | No |
| 1000Base-T | Yes |
| 10GBase-T | Yes |
Features
Facts about "Xeon D-1518 - Intel"
| l1d$ description | 8-way set associative + |
| l1i$ description | 8-way set associative + |
| l2$ description | 8-way set associative + |