Revision as of 02:08, 23 January 2016

Motorola MC14500 Family
Developer	Motorola
Manufacturer	Motorola
Type	microprocessors
Production	1976-1996
Architecture	1-bit, Harvard
ISA	MC14500
Word size	1 bit 0.125 octets 0.25 nibbles
Technology	CMOS
Clock	10 kHz-1 MHz
Package	DIP16

The MC14500 was a family of 1-bit task-oriented microprocessor chipsets designed by Motorola in the late 1970s intended to replace older relay-based ladder logic as a cheap programmable logic controller. Production continued well into the 1990s.

Members

Architecture

The MC14500B is a true 1-bit microprocessor - all operations are done on single-bit operands. The MC14500B comes with an internal clock that may be controlled via an external resistor. While designed to run at 1 MHz, it may be tuned down to 10 KHz or hooked up to an external clock altogether.

The MC14500B does not include any on-chip memory nor a program counter. A program counter is not provided because this MPU has no notion of memory at all, and by extension no notion of addresses. It implements an early Harvard architecture type of flow where separate instruction lines and data lines are fed to it. Individual instructions and values are fed in each clock cycle and the result can be read via a number of output lines. Typically a PROM chip such as the MCM7641 and PC such as the MC145168 were used to form a complete system. Because this was done externally, in theory at least, this MPU can support any amount of memory needed.

The MC14500B has a number of output lines to help facilitate subroutine returns, branching, conditional, and general purpose I/O. However since there are no built-in support for memory or addressing, they have to be dealt with externally, possibly with some glue chips.

ISA

Main article: MC14500 ISA

The MC14500B has a single register (the result register) and supports 16 different operations.

Documents

• Motorola MC14500B Industial Control Unit Handbook

See also

• SBA