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| {{\|SBA-1}} || 120x1 bits ||  || 31 || external storage
 
| {{\|SBA-1}} || 120x1 bits ||  || 31 || external storage
 
|-
 
|-
−
| {{\|SBA-2}} || 120x1 bits || 2048x8 bits || 31 ||
+
| {{\|SBA-2}} || 120x1 bits || 2048x8 bits || 31 || ?ever released?
 
|}
 
|}
 +
 +
== Architecture ==
 +
The SBA family had 8-bit instructions of two types: with immediate and without [[immediate value]].
 +
 +
* With immediate: The 5 [[MSB]]s are reserved for the address, but only up to the 30th address. The opcode is stored in the 3 LSBs.
 +
: <span style="border: 1px solid black; padding: 3px;">{{bin|00000}}-{{bin|11101}}</span><span style="border: 1px solid black;  padding: 3px;">{{bin|000}}-{{bin|111}}</span>
 +
* Without immediate: Addresses 30 and 31 are reserved for extended instructions of 8 bits.
 +
: <span style="border: 1px solid black; padding: 3px;">{{bin|11110000}}-{{bin|11111111}}</span>
 +
 +
This scheme allows for 30 addresses and 24 instructions (8 operating on [[immediate value]]s and 16 without immediates).
 +
 +
=== Stack ===
 +
{{empty section}}
 +
 +
=== Instruction Set ===
 +
{{isa
 +
| title    = SBA ISA
 +
| listing  =
 +
{{inst|mn=ANDIN  |op={{bin|AAAAA000}} |act={{l|and|In[AAAAA]|Stack[Top]}}}}
 +
{{inst|mn=NANDIN  |op={{bin|AAAAA001}} |act={{l|and|{{l|onot|In[AAAAA]}}|Stack[Top]}}}}
 +
{{inst|mn=ANDSS  |op={{bin|AAAAA010}} |act={{l|and|Store[AAAAA]|Stack[Top]}}}}
 +
{{inst|mn=NANDSS  |op={{bin|AAAAA011}} |act={{l|and|{{l|onot|Store[AAAAA]}}|Stack[Top]}}}}
 +
{{inst|mn=ASP1    |op={{bin|AAAAA100}} |act={{l|and|Store[AAAAA]|Stack[Top]}} ; PUSH(1)}}
 +
{{inst|mn=NASP1  |op={{bin|AAAAA101}} |act={{l|and|{{l|onot|Store[AAAAA]}}|Stack[Top]}} ; PUSH(1)}}
 +
{{inst|mn=STORE  |op={{bin|AAAAA110}} |act=Store[AAAAA] = Stack[Top] ; Stack[Top] = 1}}
 +
{{inst|mn=OUTPUT  |op={{bin|AAAAA111}} |act=Out[AAAAA] = Stack[Top] ; Stack[Top] = 1}}
 +
{{inst|mn=RESTART |op={{bin|11110000}} |act=restarts evaluation of program}}
 +
{{inst|mn=INVERT  |op={{bin|11110001}} |act=Stack[Top] = {{l|onot|Stack[Top]}}}}
 +
{{inst|mn=PAGE    |op={{bin|11110010}} |act=Change page}}
 +
{{inst|mn=HOME    |op={{bin|11110011}} |act=Back to home page}}
 +
{{inst|mn=PUSH0  |op={{bin|11110100}} |act=PUSH(0)}}
 +
{{inst|mn=PUSH1  |op={{bin|11110101}} |act=PUSH(1)}}
 +
{{inst|mn=PUSHC  |op={{bin|11110110}} |act=PUSH(Stack[Top])}}
 +
{{inst|mn=POP    |op={{bin|11110111}} |act=POP()}}
 +
{{inst|mn=AND    |op={{bin|11111000}} |act=Stack[Top] = {{l|and|Stack[Top]|Stack[Top-1]}}}}
 +
{{inst|mn=OR      |op={{bin|11111001}} |act=Stack[Top] = {{l|or|Stack[Top]|Stack[Top-1]}}}}
 +
{{inst|mn=EXOR    |op={{bin|11111010}} |act=Stack[Top] = {{l|xor|Stack[Top]|Stack[Top-1]}}}}
 +
{{inst|mn=COMP    |op={{bin|11111011}} |act=}}
 +
{{inst|mn=PAND    |op={{bin|11111100}} |act={{l|and|PUSH(Stack[Top]|Stack[Top-1])}} ; Stack[Top] = 1}}
 +
{{inst|mn=POR    |op={{bin|11111101}} |act={{l|or|PUSH(Stack[Top]|Stack[Top-1])}} ; Stack[Top] = 1}}
 +
{{inst|mn=PEXOR  |op={{bin|11111110}} |act={{l|xor|PUSH(Stack[Top]|Stack[Top-1])}} ; Stack[Top] = 1}}
 +
{{inst|mn=PCOMP  |op={{bin|11111111}} |act=}}
 +
}}
  
  
 
{{stub}}
 
{{stub}}

Revision as of 03:15, 22 January 2016

GIM SBA
no photo (ic).svg
Developer General Instrument
Manufacturer General Instrument
Type microcontrollers
Production November, 1977
Architecture 1-bit
Word size 1-bit
"-bit" is not declared as a valid unit of measurement for this property.
Technology nMOS
Clock 10 kHz-800 kHz
Package DIP40

The GI SBA (Sequential Boolean Analyzer) was a family of 1-bit microcontrollers developed by General Instrument's Microelectronics division. These microcontrollers served as cheap programmable logic controllers, replacing old relay system.

Members

Part RAM ROM I/O Ports Notes
SBA 120x1 bits 1024x8 bits 31
SBA-1 120x1 bits 31 external storage
SBA-2 120x1 bits 2048x8 bits 31  ?ever released?

Architecture

The SBA family had 8-bit instructions of two types: with immediate and without immediate value.

  • With immediate: The 5 MSBs are reserved for the address, but only up to the 30th address. The opcode is stored in the 3 LSBs.
000002-1110120002-1112
  • Without immediate: Addresses 30 and 31 are reserved for extended instructions of 8 bits.
111100002-111111112

This scheme allows for 30 addresses and 24 instructions (8 operating on immediate values and 16 without immediates).

Stack

New text document.svg This section is empty; you can help add the missing info by editing this page.

Instruction Set

SBA ISA
Mnemonic
ANDINAAAAA0002In[AAAAA] · Stack[Top]
NANDINAAAAA0012In[AAAAA] · Stack[Top]
ANDSSAAAAA0102Store[AAAAA] · Stack[Top]
NANDSSAAAAA0112Store[AAAAA] · Stack[Top]
ASP1AAAAA1002Store[AAAAA] · Stack[Top] ; PUSH(1)
NASP1AAAAA1012Store[AAAAA] · Stack[Top] ; PUSH(1)
STOREAAAAA1102Store[AAAAA] = Stack[Top] ; Stack[Top] = 1
OUTPUTAAAAA1112Out[AAAAA] = Stack[Top] ; Stack[Top] = 1
RESTART111100002restarts evaluation of program
INVERT111100012Stack[Top] = Stack[Top]
PAGE111100102Change page
HOME111100112Back to home page
PUSH0111101002PUSH(0)
PUSH1111101012PUSH(1)
PUSHC111101102PUSH(Stack[Top])
POP111101112POP()
AND111110002Stack[Top] = Stack[Top] · Stack[Top-1]
OR111110012Stack[Top] = Stack[Top] + Stack[Top-1]
EXOR111110102Stack[Top] = Stack[Top] ⊕ Stack[Top-1]
COMP111110112
PAND111111002PUSH(Stack[Top] · Stack[Top-1]) ; Stack[Top] = 1
POR111111012PUSH(Stack[Top] + Stack[Top-1]) ; Stack[Top] = 1
PEXOR111111102PUSH(Stack[Top] ⊕ Stack[Top-1]) ; Stack[Top] = 1
PCOMP111111112


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