Semiconductor & Computer Engineering
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<tr><th colspan="8" style="background:#D6D6FF;">Crystal Well Processors</th></tr> | <tr><th colspan="8" style="background:#D6D6FF;">Crystal Well Processors</th></tr> | ||
| − | <tr><th>Model</th><th>Family</th><th>Microarchitecture</th><th>Launched</th><th>Cores</th><th>Threads</th><th>Frequency</th><th>Process</th></tr> | + | <tr><th>Model</th><th>[[microprocessor family|Family]]</th><th>Microarchitecture</th><th>Launched</th><th>Cores</th><th>Threads</th><th>Frequency</th><th>Process</th></tr> |
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[[Category:microprocessor models by intel]] | [[Category:microprocessor models by intel]] | ||
Revision as of 16:20, 28 December 2015
Crystal Well is the codename for the L4 cache, a discrete eDRAM silicon die, which is featured in the high-end Iris Pro-equipped Intel Haswell microprocessors. The eDRAM silicon die is separate from the main Haswell die but is packaged together with it. Crystal Well based processors started shipping in the third quarter of 2013.
Details
Crystal Well is a true 128MB L4$ which could be utilized by the core itself, not just by the Iris Pro's framebuffer. I.E. L3$ values that gets evicted go into L4$. The L4$ caches serve GPU and CPU memory accesses; memory is partitioned between the two. If the GPU is disabled, such as when a discrete GPU is installed, the L4$ will be used exclusively by the CPU.
Intel has not disclosed many technical specs regarding how the Crystal Well die communicates with the main die. Intel has stated that the cache is capable of delivering 100GB/s bandwidth (50GB/s in each direction).