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{| class="wikitable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;"
−
{| class="wikitable" style="font-size: 85%; text-align: center;"
 
 
|+RDNA integrated GPU chips  
 
|+RDNA integrated GPU chips  
 
|-
 
|-
−
! style="min-width: 12em;" | Microarchitecture
+
! style="min-width: 10em;" | [[Microarchitecture]]
−
! colspan="5" | RDNA&nbsp;2
+
! colspan="5" | RDNA 2 (Navi II)
−
! colspan="2" | RDNA&nbsp;3
+
! colspan="2" | RDNA 3 (Navi III)
−
! colspan="3" | RDNA&nbsp;3.5
+
! colspan="3" | RDNA 3.5 (Navi III)
 +
|-
 +
! Introduced
 +
| Radeon<br>660M<hr>680M
 +
| Radeon<br>Graphics<br>128SP
 +
| Radeon<br>610M
 +
| Radeon<br>660M<hr>680M
 +
| Radeon<br>610M
 +
| 740M<hr>760M<hr>780M
 +
| 740M<hr>760M<hr>780M
 +
| Radeon<br>880M<hr>890M
 +
| 8040S<hr>8050S<hr>8060S
 +
| Radeon<br>860M
 
|-
 
|-
−
! [[Code name]]
+
! Code name
 
| Rembrandt  
 
| Rembrandt  
 
| Raphael  
 
| Raphael  
 
| Mendocino  
 
| Mendocino  
−
|Rembrandt-R
+
| Rembrandt-R
 
| Dragon Range
 
| Dragon Range
 
| Phoenix  
 
| Phoenix  
 
| Hawk Point
 
| Hawk Point
−
| ''Strix Point<ref>{{Cite web |title=AMD Strix Point |url=https://www.techpowerup.com/gpu-specs/amd-strix-point.g1079 |access-date=September 7, 2024 |website=TechPowerUp}}</ref><ref>{{Cite web |title=AMD Details the Radeon 890M RDNA 3.5 iGPU of "Strix Point" a bit More |url=https://www.techpowerup.com/324874/amd-details-the-radeon-890m-rdna-3-5-igpu-of-strix-point-a-bit-more |access-date=September 7, 2024 |website=TechPowerUp}}</ref>''
+
| ''Strix Point'' <ref>{{cite book |title=AMD Strix Point GPU Specs |url=https://www.techpowerup.com/gpu-specs/amd-strix-point.g1079 |access-date=September 7, 2024 |website=TechPowerUp}}</ref> <ref>{{cite book |title=AMD Details the Radeon 890M RDNA 3.5 iGPU of "Strix Point" a bit More |url=https://www.techpowerup.com/324874/amd-details-the-radeon-890m-rdna-3-5-igpu-of-strix-point-a-bit-more |access-date=September 7, 2024 |website=TechPowerUp}}</ref>
−
|''Strix Halo''<ref>{{Cite web |date=2025-10-09 |title=AMD Strix Halo GPU Specs |url=https://www.techpowerup.com/gpu-specs/amd-strix-halo.g1096 |access-date=2025-10-09 |website=TechPowerUp |language=en}}</ref>
+
| ''Strix Halo'' <ref>{{cite book |title=AMD Strix Halo GPU Specs |url=https://www.techpowerup.com/gpu-specs/amd-strix-halo.g1096 |access-date=2025-10-09 |website=TechPowerUp}}</ref>
−
|''Krackan Point''<ref>{{Cite web |date=2025-10-09 |title=AMD Krackan Point GPU Specs |url=https://www.techpowerup.com/gpu-specs/amd-krackan-point.g1092 |access-date=2025-10-09 |website=TechPowerUp |language=en}}</ref>
+
|''Krackan Point'' <ref>{{cite book |title=AMD Krackan Point GPU Specs |url=https://www.techpowerup.com/gpu-specs/amd-krackan-point.g1092 |access-date=2025-10-09 |website=TechPowerUp}}</ref>
 
|-
 
|-
−
! LLVM target<ref>{{cite web |title=User Guide for AMDGPU Backend — LLVM 22.0.0git documentation |url=https://llvm.org/docs/AMDGPUUsage.html |website=llvm.org}}</ref><ref>{{cite web |title=Accelerator and GPU hardware specifications — ROCm Documentation |url=https://rocm.docs.amd.com/en/latest/reference/gpu-arch-specs.html |website=rocm.docs.amd.com}}</ref>
+
! LLVM target <ref>{{cite book |title=User Guide for AMD GPU Backend — LLVM 22.0.0 git Documentation |url=https://llvm.org/docs/AMDGPUUsage.html |website=llvm.org}}</ref> <ref>{{cite book |title=Accelerator and GPU hardware specifications — ROCm Documentation |url=https://rocm.docs.amd.com/en/latest/reference/gpu-arch-specs.html |website=rocm.docs.amd.com}}</ref>
 
| gfx1035
 
| gfx1035
 
| gfx1036
 
| gfx1036
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| gfx1037
 
| gfx1037
 
| colspan="2" | gfx1103
 
| colspan="2" | gfx1103
−
| gfx115{0,1}
+
| gfx1150 (1)
 
| gfx1151
 
| gfx1151
 
| gfx1152
 
| gfx1152
 
|-
 
|-
−
! [[Semiconductor device fabrication|Fab]]
+
! Fab process
−
| colspan="5" |TSMC&nbsp;[[7 nm process|N6]]
+
| colspan="5" | [[TSMC]] [[7 nm process|N6]]
 
| colspan="2" |
 
| colspan="2" |
−
| colspan="3" |TSMC&nbsp;N4
+
| colspan="3" | [[TSMC]] [[5 nm process|N4]]
 
|-
 
|-
 
! Package
 
! Package
−
| colspan="5" |[[Integrated circuit|Monolithic]]
+
| colspan="5" | Monolithic
 
| colspan="2" |
 
| colspan="2" |
−
| Monolithic{{Efn|name=onechip|Everything (including CPU) on one die}}
+
| Monolithic  
−
| Semi-MCM{{Efn|GPU integrated into IO die; CPU cores on two dies}}
+
| Semi-MCM  
−
| Monolithic{{Efn|name=onechip}}
+
| Monolithic  
 
|-
 
|-
 
! Die&nbsp;size (mm<sup>2</sup>)
 
! Die&nbsp;size (mm<sup>2</sup>)
 
| || ||
 
| || ||
−
| || || || || {{TBA}} ||308||{{TBA}}
+
| || || || || TBA || 308 || TBA
 
|-
 
|-
−
! Transistors (billions)
+
! Workgroup processors <br>(WGP)
 
| || ||
 
| || ||
−
| || || || || colspan=3 {{TBA}}
+
| || || || || 8 || 20 || 4
 
|-
 
|-
−
! Transistor density<br />(MTr/mm<sup>2</sup>)
+
! Compute units (CU)
 
| || ||
 
| || ||
−
| || || || || colspan=3 {{TBA}}
+
| || || ||  
−
|-
+
| 16 || 40 || 8
−
! Shader engines
 
−
| || colspan="2" |
 
−
| || || ||
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
! Shader arrays
 
−
| || colspan="2" |
 
−
| || || ||
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
! Workgroup processors
+
! Stream processors <br>(Cores)
−
| || ||
+
| 384<hr>768 || 128 || 128
−
| || || || || 8 ||20||4
+
| 384<hr>768 || 128 || 256<hr>512<hr>768 || 256<hr>512<hr>768
 +
| 768<hr>1024 || 2560 || 512
 
|-
 
|-
−
! Compute units
+
! Texture mapping units <br>(TMU)
−
| || ||
+
| 24<hr>48 || 8 || 8
−
| || || || || 16 ||40||8
+
| 24<hr>48 || 8 || 16<hr>32<hr>48 || 16<hr>32<hr>48
 +
| 48<hr>64 || 160 || 32
 
|-
 
|-
−
! [[Unified shader model|Stream processors]]
+
! Render output units <br>(ROP)
−
| || ||
+
| 16<hr>32 || 8 || 4
−
| || || || || 1024 ||2560||512
+
| 16<hr>32 || 4 || 8<hr>16<hr>32 || 8<hr>16<hr>32
 +
| 16<hr>32 || 64 ||8
 
|-
 
|-
−
! [[Texture mapping unit]]s
+
! RT accelerators
 
| || ||
 
| || ||
−
| || || || || 64 ||160||32
+
| || || ||  
 +
| 16 || 40 || 8
 
|-
 
|-
−
! [[Render output unit]]s
+
! [[AI accelerator]]s
−
|
 
−
| colspan="2" |
 
−
| || || || || 32 ||64 ||8
 
−
|-
 
−
! [[Ray tracing (graphics)|RT accelerators]]
 
−
| || ||
 
−
| || || || || 16 ||40||8
 
−
|-
 
−
! [[AI accelerator]]s{{efn|GPU matrix-multiplication units, not to be confused with the XDNA NPU.}}
 
 
| colspan="5" |
 
| colspan="5" |
−
| || || 32 || 80 || 16  
+
| ||  
 +
| 32 || 80 || 16  
 
|-
 
|-
−
! L0&nbsp;[[Cache (computing)#Examples of hardware caches|cache]] (KB)
+
! L0&nbsp;cache (KB)
−
| colspan="5" |32&nbsp;per Workgroup processor (WGP)
+
| colspan="5" | 32 KB per WGP (Workgroup processor)
−
| colspan="5" | 64&nbsp;per WGP
+
| colspan="5" | 64 KB per WGP
 
|-
 
|-
 
! L1&nbsp;cache (KB)
 
! L1&nbsp;cache (KB)
−
| colspan="5" |128&nbsp;per Shader array (SA)
+
| colspan="5" | 128 KB per SA (Shader array)
−
| colspan="5" | 256&nbsp;per SA
+
| colspan="5" | 256 KB per SA
 
|-
 
|-
 
! L2&nbsp;cache (MB)
 
! L2&nbsp;cache (MB)
 
| || ||
 
| || ||
−
| || || ||
+
| || || || || 2 || 8 || 1
−
|2
 
−
|8
 
−
|1
 
 
|-
 
|-
 
! L3&nbsp;cache (MB)
 
! L3&nbsp;cache (MB)
 
| || ||
 
| || ||
−
| || || || || 0 || 32{{efn|MALL cache is dedicated to GPU}} || 0  
+
| || || || || 0 || 32 || 0  
 
|-
 
|-
 
! Memory type
 
! Memory type
−
|DDR5/LPDDR5
+
| DDR5 /<br>LPDDR5
−
|DDR5
+
| GDDR6
−
|LPDDR5
+
| LPDDR5
−
|DDR5/LPDDR5
+
| DDR5 /<br>LPDDR5
−
|DDR5
+
| GDDR6
−
| colspan="5" |DDR5/LPDDR5(X)
+
| colspan="5" | DDR5 / LPDDR5(X)
 
|-
 
|-
−
! Memory bus (bits){{Efn|1=Dual-channel DDR5 provides 2*64=128 bits of width.}}
+
! Memory bus (bits)  
−
| colspan="5" | 128 || colspan="2" | 128  
+
| colspan="3" | 128 || colspan="2" | 128 || colspan="2" | 128  
−
|128|| 128/256 || 128  
+
| 128 || 128 / 256 || 128  
 
|-
 
|-
 
! Display Core Next
 
! Display Core Next
 
| colspan="2" | ||
 
| colspan="2" | ||
−
| || || colspan="2" | || 3.1.4 ||3.5.0||3.5.0
+
| || || colspan="2" | || 3.1.4 || 3.5.0 || 3.5.0
 
|-
 
|-
−
! [[Video Core Next]]
+
! Video Core Next
 
| colspan="2" | ||
 
| colspan="2" | ||
−
| || || colspan="2" | || 4.0.2 ||4.0.5 ||4.0.5
+
| || || colspan="2" | || 4.0.2 || 4.0.5 || 4.0.5
 
|-
 
|-
 
! Launch
 
! Launch
−
| {{dts|2022|January||format=my|abbr=on}}
+
| January <br>2022
−
| colspan="2" | {{dts|2022|September||format=my|abbr=on}}
+
| colspan="2" | September <br>2022
−
| colspan="3" | {{dts|2023|January||format=my|abbr=on}}
+
| colspan="3" | January <br>2023
−
| {{dts|2023|December||format=my|abbr=on}}
+
| December <br>2023
−
| {{dts|2024|July||format=my|abbr=on}}
+
| July <br>2024
−
| {{dts|2025|January||format=my|abbr=on}}
+
| January <br>2025
−
| {{dts|2025|March||format=my|abbr=on}}
+
| March <br>2025
−
|-
 
−
! Introduced with
 
−
| style="vertical-align:top; text-align: left;" | {{ubl|660M|680M}}
 
−
| style="vertical-align:top; text-align: left;" | Radeon<br />Graphics
 
−
| style="vertical-align:top; text-align: left;" | 610M
 
−
| style="vertical-align:top; text-align: left;" | {{ubl|660M|680M}}
 
−
| style="vertical-align:top; text-align: left;" | 610M
 
−
| style="vertical-align:top; text-align: left;" | {{ubl|740M|760M|780M}}
 
−
| style="vertical-align:top; text-align: left;" | {{ubl|740M|760M|780M}}
 
−
| style="vertical-align:top; text-align: left;" | {{ubl|[[List of AMD Ryzen processors#Strix Point mobile|880M]]|[[List of AMD Ryzen processors#Strix Point mobile|890M]]}}
 
−
| style="vertical-align:top; text-align: left;" | {{ubl|[[List of AMD Ryzen processors#Strix Halo mobile|8040S]]|[[List of AMD Ryzen processors#Strix Halo mobile|8050S]]|[[List of AMD Ryzen processors#Strix Halo mobile|8060S]]}}
 
−
| style="vertical-align:top; text-align: left;" | 860M
 
 
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== References ==
 
== References ==

Revision as of 10:00, 5 November 2025

Edit Values
Navi µarch
General Info
Arch TypeGPU
DesignerAMD
ManufacturerTSMC
Introduction2018
Process7 nm
Succession

Navi is the successor to Vega, a 7 nm high-performance graphics processing unit microarchitecture for the gaming market.

Architecture

amd gpu roadmap.png

Key changes from Vega

Models
  • Navi • Radeon RX 5000 series
  • Navi 2x • Radeon RX 6000 series
  • Navi 3x • Radeon RX 7000 series

Generation

AMD Navi II IGP (7)
Name Family Bus Memory GPU Clock Memory Clock Cores / TMUs / ROPs Release
Radeon 610M Mendocino PCIe 4.0 x8 System Shared / DDR5 1900 MHz System Shared 128 / 8 / 4 Sep 20, 2022
Radeon 610M Dragon Range PCIe 4.0 x8 System Shared / GDDR6 2200 MHz System Shared 128 / 8 / 4 Jan 3, 2023
Radeon 660M Rembrandt PCIe 4.0 x8 System Shared / DDR5 1900 MHz System Shared 384 / 24 / 16 Jan 4, 2022
Radeon 660M Rembrandt+ PCIe 4.0 x8 System Shared / DDR5 1900 MHz System Shared 384 / 24 / 16 Jan 3, 2023
Radeon 680M Rembrandt PCIe 4.0 x8 System Shared / DDR5 2200 MHz System Shared 768 / 48 / 32 Jan 4, 2022
Radeon 680M Rembrandt+ PCIe 4.0 x8 System Shared / DDR5 2200 MHz System Shared 768 / 48 / 32 Jan 3, 2023
Radeon Graphics 128SP Raphael PCIe 4.0 x8 System Shared / GDDR6 2200 MHz System Shared 128 / 8 / 8 Sep 27, 2022
AMD Navi III IGP (12)
Name Family Bus Memory GPU Clock Memory Clock Cores / TMUs / ROPs Release
Radeon 740M Phoenix PCIe 4.0 x8 System Shared / DDR5 2500 MHz System Shared 256 / 16 / 8 Jan 4th, 2023
Radeon 740M Hawk Point PCIe 4.0 x8 System Shared / DDR5 2800 MHz System Shared 256 / 16 / 8 Dec 6, 2023
Radeon 740M Phoenix2 PCIe 4.0 x8 System Shared / DDR5 2800 MHz System Shared 256 / 16 / 8 Jan 31, 2024
Radeon 760M Phoenix PCIe 4.0 x8 System Shared / DDR5 2600 MHz System Shared 512 / 32 / 16 Jan 4, 2023
Radeon 760M Hawk Point PCIe 4.0 x8 System Shared / DDR5 2600 MHz System Shared 512 / 32 / 16 Dec 6, 2023
Radeon 760M Phoenix PCIe 4.0 x8 System Shared / DDR5 2600 MHz System Shared 512 / 32 / 16 Jan 31, 2024
Radeon 780M Phoenix PCIe 4.0 x8 System Shared / DDR5 2700 MHz System Shared 768 / 48 / 32 Jan 4, 2023
Radeon 780M Hawk Point PCIe 4.0 x8 System Shared / DDR5 2700 MHz System Shared 768 / 48 / 32 Dec 6, 2023
Radeon 780M Phoenix PCIe 4.0 x8 System Shared / DDR5 2900 MHz System Shared 768 / 48 / 32 Jan 31, 2024
Radeon 860M Krackan Point PCIe 4.0 x8 System Shared / DDR5 3000 MHz System Shared 512 / 32 / 8 Mar 15, 2025
Radeon 880M Strix Point PCIe 4.0 x8 System Shared / DDR5 2900 MHz System Shared 768 / 48 / 16 Jul 15, 2024
Radeon 890M Strix Point PCIe 4.0 x8 System Shared / DDR5 2900 MHz System Shared 1024 / 64 / 32 Jul 15, 2024

Comparison of RDNA chips

RDNA integrated GPU chips
Microarchitecture RDNA 2 (Navi II) RDNA 3 (Navi III) RDNA 3.5 (Navi III)
Introduced Radeon
660M
680M 		Radeon
Graphics
128SP 		Radeon
610M 		Radeon
660M
680M 		Radeon
610M 		740M
760M
780M 		740M
760M
780M 		Radeon
880M
890M 		8040S
8050S
8060S 		Radeon
860M
Code name Rembrandt Raphael Mendocino Rembrandt-R Dragon Range Phoenix Hawk Point Strix Point [1] [2] Strix Halo [3] Krackan Point [4]
LLVM target [5] [6] gfx1035 gfx1036 gfx1037 gfx1035 gfx1037 gfx1103 gfx1150 (1) gfx1151 gfx1152
Fab process TSMC N6 TSMC N4
Package Monolithic Monolithic Semi-MCM Monolithic
Die size (mm2) TBA 308 TBA
Workgroup processors
(WGP) 		8 20 4
Compute units (CU) 16 40 8
Stream processors
(Cores) 		384
768 		128 128 384
768 		128 256
512
768 		256
512
768 		768
1024 		2560 512
Texture mapping units
(TMU) 		24
48 		8 8 24
48 		8 16
32
48 		16
32
48 		48
64 		160 32
Render output units
(ROP) 		16
32 		8 4 16
32 		4 8
16
32 		8
16
32 		16
32 		64 8
RT accelerators 16 40 8
AI accelerators 32 80 16
L0 cache (KB) 32 KB per WGP (Workgroup processor) 64 KB per WGP
L1 cache (KB) 128 KB per SA (Shader array) 256 KB per SA
L2 cache (MB) 2 8 1
L3 cache (MB) 0 32 0
Memory type DDR5 /
LPDDR5 		GDDR6 LPDDR5 DDR5 /
LPDDR5 		GDDR6 DDR5 / LPDDR5(X)
Memory bus (bits) 128 128 128 128 128 / 256 128
Display Core Next 3.1.4 3.5.0 3.5.0
Video Core Next 4.0.2 4.0.5 4.0.5
Launch January
2022 		September
2022 		January
2023 		December
2023 		July
2024 		January
2025 		March
2025

References

  • AMD 2017 Financial Analyst Day, May 16, 2017

See also

  • ↑ AMD Strix Point GPU Specs.
  • ↑ AMD Details the Radeon 890M RDNA 3.5 iGPU of "Strix Point" a bit More.
  • ↑ AMD Strix Halo GPU Specs.
  • ↑ AMD Krackan Point GPU Specs.
  • ↑ User Guide for AMD GPU Backend — LLVM 22.0.0 git Documentation.
  • ↑ Accelerator and GPU hardware specifications — ROCm Documentation.
    • Retrieved from "https://en.wikichip.org/w/index.php?title=amd/microarchitectures/navi&oldid=103922"
    Facts about "Navi - Microarchitectures - AMD"
    RDF feed
    codenameNavi +
    designerAMD +
    first launched2018 +
    full page nameamd/microarchitectures/navi +
    instance ofmicroarchitecture +
    manufacturerTSMC +
    microarchitecture typeGPU +
    nameNavi +
    process7 nm (0.007 μm, 7.0e-6 mm) +