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Difference between revisions of "hisilicon/kirin/980"
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{{hisil title|Kirin 980}}
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== Overview ==
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{{chip
 
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|future=Yes
 
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|name=Kirin 980
 
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|no image=Yes
 
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|designer=HiSilicon
 
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|designer 2=ARM Holdings
 
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|manufacturer=TSMC
 
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|model number=980
 
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|market=Mobile
 
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|first announced=August 31, 2018
 
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|first launched=August 31, 2018
 
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|family=Kirin
 
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|frequency=2,600 MHz
 
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|frequency 2=1,920 MHz
 
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|frequency 3=1,800 MHz
 
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|isa=ARMv8
 
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|isa family=ARM
 
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|microarch=Cortex-A76
 
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|microarch 2=Cortex-A55
 
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|core name=Cortex-A76
 
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|core name 2=Cortex-A55
 
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|process=7 nm
 
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|transistors=6,900,000,000
 
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|technology=CMOS
 
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|die size=74.13mm²
 
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|word size=64 bit
 
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|core count=8
 
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|thread count=8
 
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}}
 
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'''Kirin 980''' is a {{arch|64}} high-performance mobile [[ARM]] [[LTE]] SoC designed by [[HiSilicon]] and introduced in late 2018. Fabricated on TSMC's [[7 nm process]], the 980 incorporates four [[big cores|big]] {{armh|Cortex-A76|l=arch}} cores operating at up to 2.6 GHz along with four [[little cores|little]] {{armh|Cortex-A55|l=arch}} cores operating at up to 1.8 GHz. This SoC has an LTE modem supporting 1.4 Gbps download (Cat21), incorporates an ARM {{armh|Mali-G76}}, and supports LPDDR4X-4266 memory.
 
  
 
== Overview ==
 
== Overview ==

Revision as of 13:53, 8 December 2022

Overview

Overview

Cache

Main articles: Cortex-A55 § Cache and Cortex-A76 § Cache


For the Cortex-A76:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
4x64 KiB  
L1D$256 KiB
262,144 B
0.25 MiB
4x64 KiB  
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  4x512 KiB  

For the Cortex-A55:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  4x128 KiB  


Memory controller

The Kirin 980 supports 4-channel LPDDR4X up to 2133 MHz. Each channel supports at most two ranks.

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-4266
Supports ECCNo
Max Mem8 GiB
Controllers1
Channels4
Width16 bit
Max Bandwidth31.78 GiB/s
32,542.72 MiB/s
34.124 GB/s
34,123.515 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Double 15.89 GiB/s
Quad 31.78 GiB/s

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G76
DesignerARM Holdings
Execution Units10Max Displays2
Frequency720 MHz
0.72 GHz
720,000 KHz
OutputDSI
Standards
DirectX12
OpenCL1.2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0

Wireless

  • LTE Modem
    • DL: Up to User Equipment (UE) category 21
      • Downlink of up to 1.4 Gbps (4x4 MIMO + 256QAM 3CC CA = 1.2 Gbps, 2x2 MIMO + 256QAM + 1CC = 200 Mbps)
    • UL: Up to User Equipment (UE) category 18
      • Uplink of up to 200 Mbps (2x2 MIMO, 256-QAM, 1x20MHz CA)
  • Wi-Fi 802.11 ac
  • Bluetooth 5
  • NFC
  • GPS / A-GPS / GLONASS / BDS

Utilizing devices

  • Huawei P30
  • Huawei P30 Pro
  • Huawei Mate 20
  • Huawei Mate 20 Pro
  • Huawei Mate 20 X
  • Huawei Mate 20 X 5G
  • Huawei Mate 20 RS Porsche Design
  • Huawei Nova 5T
  • Honor Magic 2
  • Honor View 20 / V20
  • Huawei Mate X
  • Huawei Honor 20
  • Huawei Honor 20 Pro
  • Huawei Mediapad M6 8.4
  • Huawei Mediapad M6 10.8
  • Huawei Nova 5 Pro

Bibliography

  • Huawei Kirin 980 Keynote, 2018 IFA
Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/kirin/980&oldid=100999"
Facts about "Kirin 980 - HiSilicon"
RDF feed
has ecc memory supportfalse +
integrated gpuMali-G76 +
integrated gpu base frequency720 MHz (0.72 GHz, 720,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units10 +
l1$ size512 KiB (524,288 B, 0.5 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ size256 KiB (262,144 B, 0.25 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l1i$ size256 KiB (262,144 B, 0.25 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
max memory bandwidth31.78 GiB/s (32,542.72 MiB/s, 34.124 GB/s, 34,123.515 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels4 +
supported memory typeLPDDR4X-4266 +
used byHuawei P30 +, Huawei P30 Pro +, Huawei Mate 20 +, Huawei Mate 20 Pro +, Huawei Mate 20 X +, Huawei Mate 20 X 5G +, Huawei Mate 20 RS Porsche Design +, Huawei Nova 5T +, Honor Magic 2 +, Honor View 20 / V20 +, Huawei Mate X +, Huawei Honor 20 +, Huawei Honor 20 Pro +, Huawei Mediapad M6 8.4 +, Huawei Mediapad M6 10.8 + and Huawei Nova 5 Pro +