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Difference between revisions of "intel/microarchitectures/gracemont"
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* Core | * Core | ||
** Larger Level 1 instruction cache - 64KB per core from 32KB per core | ** Larger Level 1 instruction cache - 64KB per core from 32KB per core | ||
| − | |||
* Memory | * Memory | ||
** DDR5 (from DDR4) | ** DDR5 (from DDR4) | ||
* I/O | * I/O | ||
** PCIe 4.0 (from 3.0) | ** PCIe 4.0 (from 3.0) | ||
Revision as of 08:07, 2 June 2021
| Edit Values | |
| Gracemont µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2021 |
| Process | 10 nm |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, UMIP, GFNI-SSE, CLWB, ENCLV, SHA |
| Succession | |
Gracemont is Intel's successor to Tremont, a 10 nm microarchitecture for ultra-low power devices and microservers.
Codenames
| Platform | Core Name | PCH |
|---|---|---|
| Grand Ridge |
Process Technology
Gracemont is designed to take advantage of Intel's 10 nm process.
Architecture
Key changes from Tremont
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
- Core
- Larger Level 1 instruction cache - 64KB per core from 32KB per core
- Memory
- DDR5 (from DDR4)
- I/O
- PCIe 4.0 (from 3.0)
Facts about "Gracemont - Microarchitectures - Intel"
| codename | Gracemont + |
| designer | Intel + |
| first launched | 2021 + |
| full page name | intel/microarchitectures/gracemont + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Gracemont + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |