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Difference between revisions of "intel/xeon silver/4215r"
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{{intel title|Xeon Silver 4215R}} | {{intel title|Xeon Silver 4215R}} | ||
| − | {{chip}} | + | {{chip |
| + | |name=Xeon Silver 4215R | ||
| + | |image=cascade lake sp (front).png | ||
| + | |designer=Intel | ||
| + | |manufacturer=Intel | ||
| + | |model number=4215R | ||
| + | |market=Server | ||
| + | |first announced=February 24, 2020 | ||
| + | |first launched=February 24, 2020 | ||
| + | |release price (tray)=$794.00 | ||
| + | |family=Xeon Silver | ||
| + | |series=4200 | ||
| + | |frequency=3,200 MHz | ||
| + | |turbo frequency1=4,000 MHz | ||
| + | |bus type=DMI 3.0 | ||
| + | |bus links=4 | ||
| + | |bus rate=8 GT/s | ||
| + | |clock multiplier=32 | ||
| + | |isa=x86-64 | ||
| + | |isa family=x86 | ||
| + | |microarch=Cascade Lake | ||
| + | |platform=Purley | ||
| + | |chipset=Lewisburg | ||
| + | |core name=Cascade Lake SP | ||
| + | |core family=6 | ||
| + | |process=14 nm | ||
| + | |technology=CMOS | ||
| + | |word size=64 bit | ||
| + | |core count=8 | ||
| + | |thread count=16 | ||
| + | |max memory=1 TiB | ||
| + | |max cpus=2 | ||
| + | |smp interconnect=UPI | ||
| + | |smp interconnect links=2 | ||
| + | |smp interconnect rate=9.6 GT/s | ||
| + | |tdp=130 W | ||
| + | |tcase min=0 °C | ||
| + | |tcase max=79 °C | ||
| + | |package name 1=intel,fclga_3647 | ||
| + | |predecessor=Xeon Silver 4215 | ||
| + | |predecessor link=intel/xeon silver/4215 | ||
| + | }} | ||
Revision as of 10:08, 28 February 2020
| Edit Values | |
| Xeon Silver 4215R | |
 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | 4215R |
| Market | Server |
| Introduction | February 24, 2020 (announced) February 24, 2020 (launched) |
| Release Price | $794.00 (tray) |
| Shop | Amazon |
| General Specs | |
| Family | Xeon Silver |
| Series | 4200 |
| Frequency | 3,200 MHz |
| Turbo Frequency | 4,000 MHz (1 core) |
| Bus type | DMI 3.0 |
| Bus rate | 4 × 8 GT/s |
| Clock multiplier | 32 |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Cascade Lake |
| Platform | Purley |
| Chipset | Lewisburg |
| Core Name | Cascade Lake SP |
| Core Family | 6 |
| Process | 14 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 8 |
| Threads | 16 |
| Max Memory | 1 TiB |
| Multiprocessing | |
| Max SMP | 2-Way (Multiprocessor) |
| Interconnect | UPI |
| Interconnect Links | 2 |
| Interconnect Rate | 9.6 GT/s |
| Electrical | |
| TDP | 130 W |
| Tcase | 0 °C – 79 °C |
| Packaging | |
| Package | FCLGA-3647 (FCLGA) |
| Dimension | 76.16 mm × 56.6 mm |
| Pitch | 0.8585 mm × 0.9906 mm |
| Contacts | 3647 |
| Socket | Socket P, LGA-3647 |
| Succession | |
Facts about "Xeon Silver 4215R - Intel"
| full page name | intel/xeon silver/4215r + |
| instance of | microprocessor + |
| ldate | 1900 + |